display/msm/qcom%2Csm6115-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14   sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21     const: qcom,sm6115-mdss
25       - description: Display AHB clock from gcc
26       - description: Display AXI clock
27       - description: Display core clock
33   "^display-controller@[0-9a-f]+$":
37         const: qcom,sm6115-dpu
39   "^dsi@[0-9a-f]+$":
44           - items:
45               - const: qcom,sm6115-dsi-ctrl
46               - const: qcom,mdss-dsi-ctrl
47           - description: Old binding, please don't use
49             const: qcom,dsi-ctrl-6g-qcm2290
51   "^phy@[0-9a-f]+$":
55         const: qcom,dsi-phy-14nm-2290
58   - compatible
63   - |
64     #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
65     #include <dt-bindings/clock/qcom,gcc-sm6115.h>
66     #include <dt-bindings/clock/qcom,rpmcc.h>
67     #include <dt-bindings/interrupt-controller/arm-gic.h>
68     #include <dt-bindings/power/qcom-rpmpd.h>
70     display-subsystem@5e00000 {
71         #address-cells = <1>;
72         #size-cells = <1>;
73         compatible = "qcom,sm6115-mdss";
75         reg-names = "mdss";
76         power-domains = <&dispcc MDSS_GDSC>;
79                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
82         interrupt-controller;
83         #interrupt-cells = <1>;
89         display-controller@5e01000 {
90             compatible = "qcom,sm6115-dpu";
93             reg-names = "mdp", "vbif";
96                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
97                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
98                      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
99                      <&dispcc DISP_CC_MDSS_ROT_CLK>,
100                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
101             clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
103             operating-points-v2 = <&mdp_opp_table>;
104             power-domains = <&rpmpd SM6115_VDDCX>;
106             interrupt-parent = <&mdss>;
110                 #address-cells = <1>;
111                 #size-cells = <0>;
116                         remote-endpoint = <&dsi0_in>;
123             compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
125             reg-names = "dsi_ctrl";
127             interrupt-parent = <&mdss>;
130             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
131                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
132                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
133                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
134                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
136             clock-names = "byte",
142 …      assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
143             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
145             operating-points-v2 = <&dsi_opp_table>;
146             power-domains = <&rpmpd SM6115_VDDCX>;
149             #address-cells = <1>;
150             #size-cells = <0>;
153                 #address-cells = <1>;
154                 #size-cells = <0>;
159                         remote-endpoint = <&dpu_intf1_out>;
172             compatible = "qcom,dsi-phy-14nm-2290";
176             reg-names = "dsi_phy",
180             #clock-cells = <1>;
181             #phy-cells = <0>;
183             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
184             clock-names = "iface", "ref";