Lines Matching +full:dispcc +full:- +full:sdm845
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SDM845 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
28 clock-names:
30 - const: iface
31 - const: core
39 interconnect-names:
43 "^display-controller@[0-9a-f]+$":
47 const: qcom,sdm845-dpu
49 "^displayport-controller@[0-9a-f]+$":
53 const: qcom,sdm845-dp
55 "^dsi@[0-9a-f]+$":
60 - const: qcom,sdm845-dsi-ctrl
61 - const: qcom,mdss-dsi-ctrl
63 "^phy@[0-9a-f]+$":
67 const: qcom,dsi-phy-10nm
70 - compatible
75 - |
76 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
77 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
78 #include <dt-bindings/clock/qcom,rpmh.h>
79 #include <dt-bindings/interrupt-controller/arm-gic.h>
80 #include <dt-bindings/power/qcom-rpmpd.h>
82 display-subsystem@ae00000 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "qcom,sdm845-mdss";
87 reg-names = "mdss";
88 power-domains = <&dispcc MDSS_GDSC>;
91 <&dispcc DISP_CC_MDSS_MDP_CLK>;
92 clock-names = "iface", "core";
95 interrupt-controller;
96 #interrupt-cells = <1>;
102 display-controller@ae01000 {
103 compatible = "qcom,sdm845-dpu";
106 reg-names = "mdp", "vbif";
109 <&dispcc DISP_CC_MDSS_AHB_CLK>,
110 <&dispcc DISP_CC_MDSS_AXI_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>,
112 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
113 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
115 interrupt-parent = <&mdss>;
117 power-domains = <&rpmhpd SDM845_CX>;
118 operating-points-v2 = <&mdp_opp_table>;
121 #address-cells = <1>;
122 #size-cells = <0>;
127 remote-endpoint = <&dsi0_in>;
134 remote-endpoint = <&dsi1_in>;
141 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
143 reg-names = "dsi_ctrl";
145 interrupt-parent = <&mdss>;
148 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
149 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
150 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
151 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
152 <&dispcc DISP_CC_MDSS_AHB_CLK>,
153 <&dispcc DISP_CC_MDSS_AXI_CLK>;
154 clock-names = "byte",
160 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
161 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
162 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
164 operating-points-v2 = <&dsi_opp_table>;
165 power-domains = <&rpmhpd SDM845_CX>;
168 phy-names = "dsi";
170 #address-cells = <1>;
171 #size-cells = <0>;
174 #address-cells = <1>;
175 #size-cells = <0>;
180 remote-endpoint = <&dpu_intf1_out>;
193 compatible = "qcom,dsi-phy-10nm";
197 reg-names = "dsi_phy",
201 #clock-cells = <1>;
202 #phy-cells = <0>;
204 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
206 clock-names = "iface", "ref";
207 vdds-supply = <&vreg_dsi_phy>;
211 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
213 reg-names = "dsi_ctrl";
215 interrupt-parent = <&mdss>;
218 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
219 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
220 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
221 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
222 <&dispcc DISP_CC_MDSS_AHB_CLK>,
223 <&dispcc DISP_CC_MDSS_AXI_CLK>;
224 clock-names = "byte",
230 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
231 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
232 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
234 operating-points-v2 = <&dsi_opp_table>;
235 power-domains = <&rpmhpd SDM845_CX>;
238 phy-names = "dsi";
240 #address-cells = <1>;
241 #size-cells = <0>;
244 #address-cells = <1>;
245 #size-cells = <0>;
250 remote-endpoint = <&dpu_intf2_out>;
263 compatible = "qcom,dsi-phy-10nm";
267 reg-names = "dsi_phy",
271 #clock-cells = <1>;
272 #phy-cells = <0>;
274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
276 clock-names = "iface", "ref";
277 vdds-supply = <&vreg_dsi_phy>;