Lines Matching +full:0 +full:x0ae94000

43   "^display-controller@[0-9a-f]+$":
49   "^displayport-controller@[0-9a-f]+$":
55   "^dsi@[0-9a-f]+$":
63   "^phy@[0-9a-f]+$":
86         reg = <0x0ae00000 0x1000>;
98         iommus = <&apps_smmu 0x880 0x8>,
99                  <&apps_smmu 0xc80 0x8>;
104             reg = <0x0ae01000 0x8f000>,
105                   <0x0aeb0000 0x2008>;
116             interrupts = <0>;
122                 #size-cells = <0>;
124                 port@0 {
125                     reg = <0>;
142             reg = <0x0ae94000 0x400>;
162             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
171             #size-cells = <0>;
175                 #size-cells = <0>;
177                 port@0 {
178                     reg = <0>;
194             reg = <0x0ae94400 0x200>,
195                   <0x0ae94600 0x280>,
196                   <0x0ae94a00 0x1e0>;
202             #phy-cells = <0>;
212             reg = <0x0ae96000 0x400>;
232             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
241             #size-cells = <0>;
245                 #size-cells = <0>;
247                 port@0 {
248                     reg = <0>;
264             reg = <0x0ae96400 0x200>,
265                   <0x0ae96600 0x280>,
266                   <0x0ae96a00 0x10e>;
272             #phy-cells = <0>;