display/msm/qcom%2Csdm845-dpu.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU on SDM845
10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16     const: qcom,sdm845-dpu
20       - description: Address offset and size for mdp register set
21       - description: Address offset and size for vbif register set
23   reg-names:
25       - const: mdp
26       - const: vbif
30       - description: Display GCC bus clock
31       - description: Display ahb clock
32       - description: Display axi clock
33       - description: Display core clock
34       - description: Display vsync clock
36   clock-names:
38       - const: gcc-bus
39       - const: iface
40       - const: bus
41       - const: core
42       - const: vsync
45   - compatible
46   - reg
47   - reg-names
48   - clocks
49   - clock-names
54   - |
55     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
56     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
57     #include <dt-bindings/power/qcom-rpmpd.h>
59     display-controller@ae01000 {
60         compatible = "qcom,sdm845-dpu";
63         reg-names = "mdp", "vbif";
66                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
67                  <&dispcc DISP_CC_MDSS_AXI_CLK>,
68                  <&dispcc DISP_CC_MDSS_MDP_CLK>,
69                  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
70         clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
72         interrupt-parent = <&mdss>;
74         power-domains = <&rpmhpd SDM845_CX>;
75         operating-points-v2 = <&mdp_opp_table>;
78             #address-cells = <1>;
79             #size-cells = <0>;
84                     remote-endpoint = <&dsi0_in>;
91                     remote-endpoint = <&dsi1_in>;