Lines Matching +full:sc7280 +full:- +full:dispcc
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 Display MDSS
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7280.
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: ahb
33 - const: core
41 interconnect-names:
45 "^display-controller@[0-9a-f]+$":
49 const: qcom,sc7280-dpu
51 "^displayport-controller@[0-9a-f]+$":
55 const: qcom,sc7280-dp
57 "^dsi@[0-9a-f]+$":
62 - const: qcom,sc7280-dsi-ctrl
63 - const: qcom,mdss-dsi-ctrl
65 "^edp@[0-9a-f]+$":
69 const: qcom,sc7280-edp
71 "^phy@[0-9a-f]+$":
76 - qcom,sc7280-dsi-phy-7nm
77 - qcom,sc7280-edp-phy
80 - compatible
85 - |
86 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
87 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
88 #include <dt-bindings/clock/qcom,rpmh.h>
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 #include <dt-bindings/interconnect/qcom,sc7280.h>
91 #include <dt-bindings/power/qcom-rpmpd.h>
93 display-subsystem@ae00000 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "qcom,sc7280-mdss";
98 reg-names = "mdss";
99 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
101 <&dispcc DISP_CC_MDSS_AHB_CLK>,
102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
103 clock-names = "iface",
108 interrupt-controller;
109 #interrupt-cells = <1>;
112 interconnect-names = "mdp0-mem";
117 display-controller@ae01000 {
118 compatible = "qcom,sc7280-dpu";
122 reg-names = "mdp", "vbif";
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130 clock-names = "bus",
137 interrupt-parent = <&mdss>;
139 power-domains = <&rpmhpd SC7280_CX>;
140 operating-points-v2 = <&mdp_opp_table>;
143 #address-cells = <1>;
144 #size-cells = <0>;
149 remote-endpoint = <&dsi0_in>;
156 remote-endpoint = <&edp_in>;
163 remote-endpoint = <&dp_in>;
170 compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
172 reg-names = "dsi_ctrl";
174 interrupt-parent = <&mdss>;
177 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
178 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
179 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
180 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
181 <&dispcc DISP_CC_MDSS_AHB_CLK>,
183 clock-names = "byte",
190 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
191 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
192 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
194 operating-points-v2 = <&dsi_opp_table>;
195 power-domains = <&rpmhpd SC7280_CX>;
198 phy-names = "dsi";
200 #address-cells = <1>;
201 #size-cells = <0>;
204 #address-cells = <1>;
205 #size-cells = <0>;
210 remote-endpoint = <&dpu_intf1_out>;
221 dsi_opp_table: opp-table {
222 compatible = "operating-points-v2";
224 opp-187500000 {
225 opp-hz = /bits/ 64 <187500000>;
226 required-opps = <&rpmhpd_opp_low_svs>;
229 opp-300000000 {
230 opp-hz = /bits/ 64 <300000000>;
231 required-opps = <&rpmhpd_opp_svs>;
234 opp-358000000 {
235 opp-hz = /bits/ 64 <358000000>;
236 required-opps = <&rpmhpd_opp_svs_l1>;
242 compatible = "qcom,sc7280-dsi-phy-7nm";
246 reg-names = "dsi_phy",
250 #clock-cells = <1>;
251 #phy-cells = <0>;
253 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
255 clock-names = "iface", "ref";
257 vdds-supply = <&vreg_dsi_supply>;
261 compatible = "qcom,sc7280-edp";
262 pinctrl-names = "default";
263 pinctrl-0 = <&edp_hot_plug_det>;
270 interrupt-parent = <&mdss>;
273 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
274 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
275 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
276 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
277 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
278 clock-names = "core_iface",
283 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
284 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
285 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
288 phy-names = "dp";
290 operating-points-v2 = <&edp_opp_table>;
291 power-domains = <&rpmhpd SC7280_CX>;
294 #address-cells = <1>;
295 #size-cells = <0>;
300 remote-endpoint = <&dpu_intf5_out>;
310 edp_opp_table: opp-table {
311 compatible = "operating-points-v2";
313 opp-160000000 {
314 opp-hz = /bits/ 64 <160000000>;
315 required-opps = <&rpmhpd_opp_low_svs>;
318 opp-270000000 {
319 opp-hz = /bits/ 64 <270000000>;
320 required-opps = <&rpmhpd_opp_svs>;
323 opp-540000000 {
324 opp-hz = /bits/ 64 <540000000>;
325 required-opps = <&rpmhpd_opp_nom>;
328 opp-810000000 {
329 opp-hz = /bits/ 64 <810000000>;
330 required-opps = <&rpmhpd_opp_nom>;
336 compatible = "qcom,sc7280-edp-phy";
345 clock-names = "aux",
348 #clock-cells = <1>;
349 #phy-cells = <0>;
352 displayport-controller@ae90000 {
353 compatible = "qcom,sc7280-dp";
361 interrupt-parent = <&mdss>;
364 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
365 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
366 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
367 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
368 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
369 clock-names = "core_iface",
374 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
375 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
376 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
378 phy-names = "dp";
380 operating-points-v2 = <&dp_opp_table>;
381 power-domains = <&rpmhpd SC7280_CX>;
383 #sound-dai-cells = <0>;
386 #address-cells = <1>;
387 #size-cells = <0>;
392 remote-endpoint = <&dpu_intf0_out>;
402 dp_opp_table: opp-table {
403 compatible = "operating-points-v2";
405 opp-160000000 {
406 opp-hz = /bits/ 64 <160000000>;
407 required-opps = <&rpmhpd_opp_low_svs>;
410 opp-270000000 {
411 opp-hz = /bits/ 64 <270000000>;
412 required-opps = <&rpmhpd_opp_svs>;
415 opp-540000000 {
416 opp-hz = /bits/ 64 <540000000>;
417 required-opps = <&rpmhpd_opp_svs_l1>;
420 opp-810000000 {
421 opp-hz = /bits/ 64 <810000000>;
422 required-opps = <&rpmhpd_opp_nom>;