Lines Matching +full:0 +full:xae90400
45 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
57 "^dsi@[0-9a-f]+$":
65 "^edp@[0-9a-f]+$":
71 "^phy@[0-9a-f]+$":
97 reg = <0xae00000 0x1000>;
114 iommus = <&apps_smmu 0x900 0x402>;
119 reg = <0x0ae01000 0x8f000>,
120 <0x0aeb0000 0x2008>;
138 interrupts = <0>;
144 #size-cells = <0>;
146 port@0 {
147 reg = <0>;
171 reg = <0x0ae94000 0x400>;
192 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
201 #size-cells = <0>;
205 #size-cells = <0>;
207 port@0 {
208 reg = <0>;
243 reg = <0x0ae94400 0x200>,
244 <0x0ae94600 0x280>,
245 <0x0ae94900 0x280>;
251 #phy-cells = <0>;
263 pinctrl-0 = <&edp_hot_plug_det>;
265 reg = <0xaea0000 0x200>,
266 <0xaea0200 0x200>,
267 <0xaea0400 0xc00>,
268 <0xaea1000 0x400>;
285 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
295 #size-cells = <0>;
297 port@0 {
298 reg = <0>;
338 reg = <0xaec2a00 0x19c>,
339 <0xaec2200 0xa0>,
340 <0xaec2600 0xa0>,
341 <0xaec2000 0x1c0>;
349 #phy-cells = <0>;
355 reg = <0xae90000 0x200>,
356 <0xae90200 0x200>,
357 <0xae90400 0xc00>,
358 <0xae91000 0x400>,
359 <0xae91400 0x400>;
376 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
383 #sound-dai-cells = <0>;
387 #size-cells = <0>;
389 port@0 {
390 reg = <0>;