display/msm/qcom%2Cmsm8998-mdss.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21     const: qcom,msm8998-mdss
25       - description: Display AHB clock
26       - description: Display AXI clock
27       - description: Display core clock
29   clock-names:
31       - const: iface
32       - const: bus
33       - const: core
39   "^display-controller@[0-9a-f]+$":
43         const: qcom,msm8998-dpu
45   "^dsi@[0-9a-f]+$":
50           - const: qcom,msm8998-dsi-ctrl
51           - const: qcom,mdss-dsi-ctrl
53   "^phy@[0-9a-f]+$":
57         const: qcom,dsi-phy-10nm-8998
60   - compatible
65   - |
66     #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
67     #include <dt-bindings/clock/qcom,rpmcc.h>
68     #include <dt-bindings/interrupt-controller/arm-gic.h>
69     #include <dt-bindings/power/qcom-rpmpd.h>
71     display-subsystem@c900000 {
72         compatible = "qcom,msm8998-mdss";
74         reg-names = "mdss";
79         clock-names = "iface", "bus", "core";
81         #address-cells = <1>;
82         #interrupt-cells = <1>;
83         #size-cells = <1>;
86         interrupt-controller;
89         power-domains = <&mmcc MDSS_GDSC>;
92         display-controller@c901000 {
93             compatible = "qcom,msm8998-dpu";
98             reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
105             clock-names = "iface", "bus", "mnoc", "core", "vsync";
107             interrupt-parent = <&mdss>;
109             operating-points-v2 = <&mdp_opp_table>;
110             power-domains = <&rpmpd MSM8998_VDDMX>;
113                 #address-cells = <1>;
114                 #size-cells = <0>;
119                         remote-endpoint = <&dsi0_in>;
126                         remote-endpoint = <&dsi1_in>;
132         dsi@c994000 {
133             compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
135             reg-names = "dsi_ctrl";
137             interrupt-parent = <&mdss>;
146             clock-names = "byte",
152             assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
153             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
155             operating-points-v2 = <&dsi_opp_table>;
156             power-domains = <&rpmpd MSM8998_VDDCX>;
159             phy-names = "dsi";
161             #address-cells = <1>;
162             #size-cells = <0>;
165                 #address-cells = <1>;
166                 #size-cells = <0>;
171                         remote-endpoint = <&dpu_intf1_out>;
184             compatible = "qcom,dsi-phy-10nm-8998";
188             reg-names = "dsi_phy",
192             #clock-cells = <1>;
193             #phy-cells = <0>;
197             clock-names = "iface", "ref";
199             vdds-supply = <&pm8998_l1>;
202         dsi@c996000 {
203             compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
205             reg-names = "dsi_ctrl";
207             interrupt-parent = <&mdss>;
216             clock-names = "byte",
222             assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
223             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
225             operating-points-v2 = <&dsi_opp_table>;
226             power-domains = <&rpmpd MSM8998_VDDCX>;
229             phy-names = "dsi";
231             #address-cells = <1>;
232             #size-cells = <0>;
235                 #address-cells = <1>;
236                 #size-cells = <0>;
241                         remote-endpoint = <&dpu_intf2_out>;
254             compatible = "qcom,dsi-phy-10nm-8998";
258             reg-names = "dsi_phy",
262             #clock-cells = <1>;
263             #phy-cells = <0>;
267             clock-names = "iface", "ref";
269             vdds-supply = <&pm8998_l1>;