Lines Matching +full:0 +full:x8f000

39   "^display-controller@[0-9a-f]+$":
45   "^dsi@[0-9a-f]+$":
53   "^phy@[0-9a-f]+$":
73         reg = <0x0c900000 0x1000>;
87         iommus = <&mmss_smmu 0>;
94             reg = <0x0c901000 0x8f000>,
95                   <0x0c9a8e00 0xf0>,
96                   <0x0c9b0000 0x2008>,
97                   <0x0c9b8000 0x1040>;
108             interrupts = <0>;
114                 #size-cells = <0>;
116                 port@0 {
117                     reg = <0>;
134             reg = <0x0c994000 0x400>;
153             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
162             #size-cells = <0>;
166                 #size-cells = <0>;
168                 port@0 {
169                     reg = <0>;
185             reg = <0x0c994400 0x200>,
186                   <0x0c994600 0x280>,
187                   <0x0c994a00 0x1e0>;
193             #phy-cells = <0>;
204             reg = <0x0c996000 0x400>;
223             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
232             #size-cells = <0>;
236                 #size-cells = <0>;
238                 port@0 {
239                     reg = <0>;
255             reg = <0x0c996400 0x200>,
256                   <0x0c996600 0x280>,
257                   <0x0c996a00 0x10e>;
263             #phy-cells = <0>;