Lines Matching +full:opp +full:- +full:180000000
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
16 - description: |
18 figure out the chip-id.
20 … - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
21 - const: qcom,adreno
22 - description: |
24 figure out the gpu-id and patch level.
26 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
27 - const: qcom,adreno
28 - description: |
30 figure out the gpu-id and patch level.
32 - pattern: '^amd,imageon-200\.[0-1]$'
33 - const: amd,imageon
37 clock-names: true
43 reg-names:
50 interrupt-names:
57 interconnect-names:
60 - const: gfx-mem
61 - const: ocmem
68 $ref: /schemas/types.yaml#/definitions/phandle-array
74 phandles to one or more reserved on-chip SRAM regions.
79 operating-points-v2: true
80 opp-table:
83 power-domains:
86 zap-shader:
90 For a5xx and a6xx devices this node contains a memory-region that
94 memory-region:
97 firmware-name:
101 "#cooling-cells":
104 nvmem-cell-names:
107 nvmem-cells:
119 - compatible
120 - reg
121 - interrupts
126 - if:
130 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
138 clock-names:
141 - const: core
143 - const: iface
145 - const: mem
147 - const: mem_iface
149 - const: alt_mem_iface
151 - const: gfx3d
153 - const: rbbmtimer
155 - const: rbcpr
161 - clocks
162 - clock-names
164 - if:
169 - qcom,adreno-610.0
170 - qcom,adreno-619.1
177 clock-names:
179 - const: core
181 - const: iface
183 - const: mem_iface
185 - const: alt_mem_iface
187 - const: gmu
189 - const: xo
192 reg-names:
195 - const: kgsl_3d0_reg_memory
196 - const: cx_dbgc
199 - clocks
200 - clock-names
206 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
211 clock-names: false
213 reg-names:
216 - const: kgsl_3d0_reg_memory
217 - const: cx_mem
218 - const: cx_dbgc
221 - |
225 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
226 #include <dt-bindings/clock/qcom,rpmcc.h>
227 #include <dt-bindings/interrupt-controller/irq.h>
228 #include <dt-bindings/interrupt-controller/arm-gic.h>
231 compatible = "qcom,adreno-330.2", "qcom,adreno";
234 reg-names = "kgsl_3d0_reg_memory";
236 clock-names = "core", "iface", "mem_iface";
242 interrupt-names = "kgsl_3d0_irq";
245 power-domains = <&mmcc OXILICX_GDSC>;
246 operating-points-v2 = <&gpu_opp_table>;
248 #cooling-cells = <2>;
252 compatible = "qcom,msm8974-ocmem";
256 reg-names = "ctrl", "mem";
260 clock-names = "core", "iface";
262 #address-cells = <1>;
263 #size-cells = <1>;
266 gpu_sram: gpu-sram@0 {
270 - |
274 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
275 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
276 #include <dt-bindings/power/qcom-rpmpd.h>
277 #include <dt-bindings/interrupt-controller/irq.h>
278 #include <dt-bindings/interrupt-controller/arm-gic.h>
279 #include <dt-bindings/interconnect/qcom,sdm845.h>
281 reserved-memory {
282 #address-cells = <2>;
283 #size-cells = <2>;
286 compatible = "shared-dma-pool";
288 no-map;
293 compatible = "qcom,adreno-630.2", "qcom,adreno";
296 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
298 #cooling-cells = <2>;
304 operating-points-v2 = <&gpu_opp_table>;
307 interconnect-names = "gfx-mem";
311 gpu_opp_table: opp-table {
312 compatible = "operating-points-v2";
314 opp-430000000 {
315 opp-hz = /bits/ 64 <430000000>;
316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
317 opp-peak-kBps = <5412000>;
320 opp-355000000 {
321 opp-hz = /bits/ 64 <355000000>;
322 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
323 opp-peak-kBps = <3072000>;
326 opp-267000000 {
327 opp-hz = /bits/ 64 <267000000>;
328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
329 opp-peak-kBps = <3072000>;
332 opp-180000000 {
333 opp-hz = /bits/ 64 <180000000>;
334 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
335 opp-peak-kBps = <1804000>;
339 zap-shader {
340 memory-region = <&zap_shader_region>;
341 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";