Lines Matching +full:sdm845 +full:- +full:gpucc
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - const: qcom,adreno-gmu-wrapper
32 reg-names:
40 clock-names:
46 - description: GMU HFI interrupt
47 - description: GMU interrupt
49 interrupt-names:
51 - const: hfi
52 - const: gmu
54 power-domains:
56 - description: CX power domain
57 - description: GX power domain
59 power-domain-names:
61 - const: cx
62 - const: gx
67 operating-points-v2: true
69 opp-table:
73 - compatible
74 - reg
75 - reg-names
76 - power-domains
77 - power-domain-names
82 - if:
87 - qcom,adreno-gmu-618.0
88 - qcom,adreno-gmu-630.2
93 - description: Core GMU registers
94 - description: GMU PDC registers
95 - description: GMU PDC sequence registers
96 reg-names:
98 - const: gmu
99 - const: gmu_pdc
100 - const: gmu_pdc_seq
103 - description: GMU clock
104 - description: GPU CX clock
105 - description: GPU AXI clock
106 - description: GPU MEMNOC clock
107 clock-names:
109 - const: gmu
110 - const: cxo
111 - const: axi
112 - const: memnoc
114 - if:
119 - qcom,adreno-gmu-635.0
120 - qcom,adreno-gmu-660.1
125 - description: Core GMU registers
126 - description: Resource controller registers
127 - description: GMU PDC registers
128 reg-names:
130 - const: gmu
131 - const: rscc
132 - const: gmu_pdc
135 - description: GMU clock
136 - description: GPU CX clock
137 - description: GPU AXI clock
138 - description: GPU MEMNOC clock
139 - description: GPU AHB clock
140 - description: GPU HUB CX clock
141 - description: GPU SMMU vote clock
142 clock-names:
144 - const: gmu
145 - const: cxo
146 - const: axi
147 - const: memnoc
148 - const: ahb
149 - const: hub
150 - const: smmu_vote
152 - if:
157 - qcom,adreno-gmu-640.1
162 - description: Core GMU registers
163 - description: GMU PDC registers
164 - description: GMU PDC sequence registers
165 reg-names:
167 - const: gmu
168 - const: gmu_pdc
169 - const: gmu_pdc_seq
171 - if:
176 - qcom,adreno-gmu-650.2
181 - description: Core GMU registers
182 - description: Resource controller registers
183 - description: GMU PDC registers
184 - description: GMU PDC sequence registers
185 reg-names:
187 - const: gmu
188 - const: rscc
189 - const: gmu_pdc
190 - const: gmu_pdc_seq
192 - if:
197 - qcom,adreno-gmu-640.1
198 - qcom,adreno-gmu-650.2
203 - description: GPU AHB clock
204 - description: GMU clock
205 - description: GPU CX clock
206 - description: GPU AXI clock
207 - description: GPU MEMNOC clock
208 clock-names:
210 - const: ahb
211 - const: gmu
212 - const: cxo
213 - const: axi
214 - const: memnoc
216 - if:
220 const: qcom,adreno-gmu-wrapper
225 - description: GMU wrapper register space
226 reg-names:
228 - const: gmu
231 - clocks
232 - clock-names
233 - interrupts
234 - interrupt-names
235 - iommus
236 - operating-points-v2
239 - |
240 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
241 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
242 #include <dt-bindings/interrupt-controller/irq.h>
243 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
251 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
253 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
254 <&gpucc GPU_CC_CXO_CLK>,
257 clock-names = "gmu", "cxo", "axi", "memnoc";
261 interrupt-names = "hfi", "gmu";
263 power-domains = <&gpucc GPU_CX_GDSC>,
264 <&gpucc GPU_GX_GDSC>;
265 power-domain-names = "cx", "gx";
268 operating-points-v2 = <&gmu_opp_table>;
272 compatible = "qcom,adreno-gmu-wrapper";
274 reg-names = "gmu";
275 power-domains = <&gpucc GPU_CX_GDSC>,
276 <&gpucc GPU_GX_GDSC>;
277 power-domain-names = "cx", "gx";