Lines Matching +full:gcc +full:- +full:qcm2290
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8996-dsi-ctrl
23 - qcom,msm8998-dsi-ctrl
24 - qcom,qcm2290-dsi-ctrl
25 - qcom,sc7180-dsi-ctrl
26 - qcom,sc7280-dsi-ctrl
27 - qcom,sdm660-dsi-ctrl
28 - qcom,sdm845-dsi-ctrl
29 - qcom,sm6115-dsi-ctrl
30 - qcom,sm6125-dsi-ctrl
31 - qcom,sm6350-dsi-ctrl
32 - qcom,sm6375-dsi-ctrl
33 - qcom,sm8150-dsi-ctrl
34 - qcom,sm8250-dsi-ctrl
35 - qcom,sm8350-dsi-ctrl
36 - qcom,sm8450-dsi-ctrl
37 - qcom,sm8550-dsi-ctrl
38 - const: qcom,mdss-dsi-ctrl
39 - enum:
40 - qcom,dsi-ctrl-6g-qcm2290
41 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
47 reg-names:
56 - bus:: Display AHB clock.
57 - byte:: Display byte clock.
58 - byte_intf:: Display byte interface clock.
59 - core:: Display core clock.
60 - core_mss:: Core MultiMedia SubSystem clock.
61 - iface:: Display AXI clock.
62 - mdp_core:: MDP Core clock.
63 - mnoc:: MNOC clock
64 - pixel:: Display pixel clock.
68 clock-names:
75 phy-names:
79 syscon-sfpb:
83 qcom,dual-dsi-mode:
89 qcom,master-dsi:
93 qcom,dual-dsi-mode enabled.
95 qcom,sync-dual-dsi:
99 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
101 assigned-clocks:
109 assigned-clock-parents:
115 power-domains:
118 operating-points-v2: true
120 opp-table:
131 $ref: /schemas/graph.yaml#/$defs/port-base
137 $ref: /schemas/media/video-interfaces.yaml#
140 data-lanes:
147 $ref: /schemas/graph.yaml#/$defs/port-base
153 $ref: /schemas/media/video-interfaces.yaml#
156 data-lanes:
163 - port@0
164 - port@1
166 avdd-supply:
170 refgen-supply:
174 vcca-supply:
178 vdd-supply:
182 vddio-supply:
184 VDD-IO regulator
186 vdda-supply:
191 - compatible
192 - reg
193 - reg-names
194 - interrupts
195 - clocks
196 - clock-names
197 - phys
198 - assigned-clocks
199 - assigned-clock-parents
200 - ports
203 - $ref: ../dsi-controller.yaml#
204 - if:
209 - qcom,apq8064-dsi-ctrl
214 clock-names:
216 - const: iface
217 - const: bus
218 - const: core_mmss
219 - const: src
220 - const: byte
221 - const: pixel
222 - const: core
224 - if:
229 - qcom,msm8916-dsi-ctrl
234 clock-names:
236 - const: mdp_core
237 - const: iface
238 - const: bus
239 - const: byte
240 - const: pixel
241 - const: core
243 - if:
248 - qcom,msm8953-dsi-ctrl
253 clock-names:
255 - const: mdp_core
256 - const: iface
257 - const: bus
258 - const: byte
259 - const: pixel
260 - const: core
262 - if:
267 - qcom,msm8226-dsi-ctrl
268 - qcom,msm8974-dsi-ctrl
273 clock-names:
275 - const: mdp_core
276 - const: iface
277 - const: bus
278 - const: byte
279 - const: pixel
280 - const: core
281 - const: core_mmss
283 - if:
288 - qcom,msm8996-dsi-ctrl
293 clock-names:
295 - const: mdp_core
296 - const: byte
297 - const: iface
298 - const: bus
299 - const: core_mmss
300 - const: pixel
301 - const: core
303 - if:
308 - qcom,msm8998-dsi-ctrl
309 - qcom,sm6125-dsi-ctrl
310 - qcom,sm6350-dsi-ctrl
315 clock-names:
317 - const: byte
318 - const: byte_intf
319 - const: pixel
320 - const: core
321 - const: iface
322 - const: bus
324 - if:
329 - qcom,sc7180-dsi-ctrl
330 - qcom,sc7280-dsi-ctrl
331 - qcom,sm8150-dsi-ctrl
332 - qcom,sm8250-dsi-ctrl
333 - qcom,sm8350-dsi-ctrl
334 - qcom,sm8450-dsi-ctrl
335 - qcom,sm8550-dsi-ctrl
340 clock-names:
342 - const: byte
343 - const: byte_intf
344 - const: pixel
345 - const: core
346 - const: iface
347 - const: bus
349 - if:
354 - qcom,sdm660-dsi-ctrl
359 clock-names:
361 - const: mdp_core
362 - const: byte
363 - const: byte_intf
364 - const: mnoc
365 - const: iface
366 - const: bus
367 - const: core_mmss
368 - const: pixel
369 - const: core
371 - if:
376 - qcom,sdm845-dsi-ctrl
377 - qcom,sm6115-dsi-ctrl
378 - qcom,sm6375-dsi-ctrl
383 clock-names:
385 - const: byte
386 - const: byte_intf
387 - const: pixel
388 - const: core
389 - const: iface
390 - const: bus
395 - |
396 #include <dt-bindings/interrupt-controller/arm-gic.h>
397 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
398 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
399 #include <dt-bindings/power/qcom-rpmpd.h>
402 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
404 reg-names = "dsi_ctrl";
406 #address-cells = <1>;
407 #size-cells = <0>;
409 interrupt-parent = <&mdss>;
418 clock-names = "byte",
426 phy-names = "dsi";
428 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
429 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
431 power-domains = <&rpmhpd SC7180_CX>;
432 operating-points-v2 = <&dsi_opp_table>;
435 #address-cells = <1>;
436 #size-cells = <0>;
441 remote-endpoint = <&dpu_intf1_out>;
448 remote-endpoint = <&sn65dsi86_in>;
449 data-lanes = <0 1 2 3>;