Lines Matching +full:0 +full:x0ae94000
130 port@0:144 enum: [ 0, 1, 2, 3 ]160 enum: [ 0, 1, 2, 3 ]163 - port@0403 reg = <0x0ae94000 0x400>;407 #size-cells = <0>;429 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;436 #size-cells = <0>;438 port@0 {439 reg = <0>;449 data-lanes = <0 1 2 3>;