display/mediatek/mediatek%2Cmerge.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display merge
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
14   Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15   inputs into one side-by-side output.
16   MERGE device node must be siblings to the central MMSYS_CONFIG node.
24       - enum:
25           - mediatek,mt8173-disp-merge
26           - mediatek,mt8195-disp-merge
27       - items:
28           - const: mediatek,mt6795-disp-merge
29           - const: mediatek,mt8173-disp-merge
37   power-domains:
40       Documentation/devicetree/bindings/power/power-domain.yaml for details.
46   clock-names:
48       - items:
49           - const: merge
50       - items:
51           - const: merge
52           - const: merge_async
54   mediatek,merge-fifo-en:
56       The setting of merge fifo is mainly provided for the display latency
57       buffer to ensure that the back-end panel display data will not be
59       According to the merge fifo settings, when the water level is detected
64   mediatek,merge-mute:
65     description: Support mute function. Mute the content of merge output.
68   mediatek,gce-client-reg:
72       defined in the header include/dt-bindings/gce/<chip>-gce.h.
73     $ref: /schemas/types.yaml#/definitions/phandle-array
82   - compatible
83   - reg
84   - power-domains
85   - clocks
90   - |
91     #include <dt-bindings/interrupt-controller/arm-gic.h>
92     #include <dt-bindings/clock/mt8173-clk.h>
93     #include <dt-bindings/power/mt8173-power.h>
96         #address-cells = <2>;
97         #size-cells = <2>;
99         merge@14017000 {
100             compatible = "mediatek,mt8173-disp-merge";
102             power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
104             clock-names = "merge";