display/mediatek/mediatek%2Cmdp-rdma.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
15   It provides real time data to the back-end panel driver, such as DSI,
24     const: mediatek,mt8195-vdo1-rdma
26   reg:
32   power-domains:
37       - description: RDMA Clock
42   mediatek,gce-client-reg:
44       The register of display function block to be set by gce. There are 4 arguments,
45       such as gce node, subsys id, offset and register size. The subsys id that is
46       mapping to the register of display function blocks is defined in the gce header
47       include/dt-bindings/gce/<chip>-gce.h of each chips.
48     $ref: /schemas/types.yaml#/definitions/phandle-array
51         - description: phandle of GCE
52         - description: GCE subsys id
53         - description: register offset
54         - description: register size
58   - compatible
59   - reg
60   - power-domains
61   - clocks
62   - iommus
63   - mediatek,gce-client-reg
68   - |
69     #include <dt-bindings/interrupt-controller/arm-gic.h>
70     #include <dt-bindings/clock/mt8195-clk.h>
71     #include <dt-bindings/power/mt8195-power.h>
72     #include <dt-bindings/gce/mt8195-gce.h>
73     #include <dt-bindings/memory/mt8195-memory-port.h>
76         #address-cells = <2>;
77         #size-cells = <2>;
80             compatible = "mediatek,mt8195-vdo1-rdma";
81             reg = <0 0x1c104000 0 0x1000>;
84             power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
86             mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;