Lines Matching +full:display +full:- +full:backend
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 designed for HDR video and graphics conversion in the external display path.
18 output the required HDR or SDR signal to the subsequent display path.
20 one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period.
26 const: mediatek,mt8195-disp-ethdr
31 reg-names:
33 - const: mixer
34 - const: vdo_fe0
35 - const: vdo_fe1
36 - const: gfx_fe0
37 - const: gfx_fe1
38 - const: vdo_be
39 - const: adl_ds
50 - description: mixer clock
51 - description: video frontend 0 clock
52 - description: video frontend 1 clock
53 - description: graphic frontend 0 clock
54 - description: graphic frontend 1 clock
55 - description: video backend clock
56 - description: autodownload and menuload clock
57 - description: video frontend 0 async clock
58 - description: video frontend 1 async clock
59 - description: graphic frontend 0 async clock
60 - description: graphic frontend 1 async clock
61 - description: video backend async clock
62 - description: ethdr top clock
64 clock-names:
66 - const: mixer
67 - const: vdo_fe0
68 - const: vdo_fe1
69 - const: gfx_fe0
70 - const: gfx_fe1
71 - const: vdo_be
72 - const: adl_ds
73 - const: vdo_fe0_async
74 - const: vdo_fe1_async
75 - const: gfx_fe0_async
76 - const: gfx_fe1_async
77 - const: vdo_be_async
78 - const: ethdr_top
80 power-domains:
85 - description: video frontend 0 async reset
86 - description: video frontend 1 async reset
87 - description: graphic frontend 0 async reset
88 - description: graphic frontend 1 async reset
89 - description: video backend async reset
91 reset-names:
93 - const: vdo_fe0_async
94 - const: vdo_fe1_async
95 - const: gfx_fe0_async
96 - const: gfx_fe1_async
97 - const: vdo_be_async
99 mediatek,gce-client-reg:
100 $ref: /schemas/types.yaml#/definitions/phandle-array
103 description: The register of display function block to be set by gce.
106 include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
110 - compatible
111 - reg
112 - clocks
113 - clock-names
114 - interrupts
115 - power-domains
116 - resets
117 - mediatek,gce-client-reg
122 - |
123 #include <dt-bindings/interrupt-controller/arm-gic.h>
124 #include <dt-bindings/clock/mt8195-clk.h>
125 #include <dt-bindings/gce/mt8195-gce.h>
126 #include <dt-bindings/memory/mt8195-memory-port.h>
127 #include <dt-bindings/power/mt8195-power.h>
128 #include <dt-bindings/reset/mt8195-resets.h>
131 #address-cells = <2>;
132 #size-cells = <2>;
134 hdr-engine@1c114000 {
135 compatible = "mediatek,mt8195-disp-ethdr";
143 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
145 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
165 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
169 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
178 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",