display/mediatek/mediatek%2Cdsi.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
12   - Jitao Shi <jitao.shi@mediatek.com>
13   - Xinlei Lee <xinlei.lee@mediatek.com>
17   drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
21   - $ref: /schemas/display/dsi-controller.yaml#
26       - enum:
27           - mediatek,mt2701-dsi
28           - mediatek,mt7623-dsi
29           - mediatek,mt8167-dsi
30           - mediatek,mt8173-dsi
31           - mediatek,mt8183-dsi
32           - mediatek,mt8186-dsi
33       - items:
34           - enum:
35               - mediatek,mt6795-dsi
36           - const: mediatek,mt8173-dsi
44   power-domains:
49       - description: Engine Clock
50       - description: Digital Clock
51       - description: HS Clock
53   clock-names:
55       - const: engine
56       - const: digital
57       - const: hs
65   phy-names:
67       - const: dphy
73       port of an attached DSI panel or DSI-to-eDP encoder chip.
76   - compatible
77   - reg
78   - interrupts
79   - power-domains
80   - clocks
81   - clock-names
82   - phys
83   - phy-names
84   - port
89   - |
90     #include <dt-bindings/clock/mt8183-clk.h>
91     #include <dt-bindings/interrupt-controller/arm-gic.h>
92     #include <dt-bindings/interrupt-controller/irq.h>
93     #include <dt-bindings/power/mt8183-power.h>
94     #include <dt-bindings/phy/phy.h>
95     #include <dt-bindings/reset/mt8183-resets.h>
98         #address-cells = <2>;
99         #size-cells = <2>;
102             compatible = "mediatek,mt8183-dsi";
105             power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
109             clock-names = "engine", "digital", "hs";
112             phy-names = "dphy";
115                     remote-endpoint = <&panel_in>;