display/mediatek/mediatek%2Cdp.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Jitao shi <jitao.shi@mediatek.com>
24       - mediatek,mt8195-dp-tx
25       - mediatek,mt8195-edp-tx
30   nvmem-cells:
34   nvmem-cell-names:
37   power-domains:
51         $ref: /schemas/graph.yaml#/$defs/port-base
56             $ref: /schemas/media/video-interfaces.yaml#
59               data-lanes:
63                   0       - For 1 lane enabled in IP.
64                   0 1     - For 2 lanes enabled in IP.
65                   0 1 2 3 - For 4 lanes enabled in IP.
69               - data-lanes
72       - port@0
73       - port@1
75   max-linkrate-mhz:
80   - compatible
81   - reg
82   - interrupts
83   - ports
84   - max-linkrate-mhz
89   - |
90     #include <dt-bindings/interrupt-controller/arm-gic.h>
91     #include <dt-bindings/power/mt8195-power.h>
93         compatible = "mediatek,mt8195-dp-tx";
95         power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
97         max-linkrate-mhz = <8100>;
100             #address-cells = <1>;
101             #size-cells = <0>;
106                     remote-endpoint = <&dp_intf0_out>;
112                     data-lanes = <0 1 2 3>;