display/mediatek/mediatek%2Caal.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11   - Philipp Zabel <p.zabel@pengutronix.de>
24       - enum:
25           - mediatek,mt8173-disp-aal
26           - mediatek,mt8183-disp-aal
27       - items:
28           - enum:
29               - mediatek,mt2712-disp-aal
30               - mediatek,mt6795-disp-aal
31           - const: mediatek,mt8173-disp-aal
32       - items:
33           - enum:
34               - mediatek,mt8186-disp-aal
35               - mediatek,mt8188-disp-aal
36               - mediatek,mt8192-disp-aal
37               - mediatek,mt8195-disp-aal
38           - const: mediatek,mt8183-disp-aal
40   reg:
46   power-domains:
49       Documentation/devicetree/bindings/power/power-domain.yaml for details.
53       - description: AAL Clock
55   mediatek,gce-client-reg:
56     description: The register of client driver can be configured by gce with
57       4 arguments defined in this property, such as phandle of gce, subsys id,
58       register offset and size. Each GCE subsys id is mapping to a client
59       defined in the header include/dt-bindings/gce/<chip>-gce.h.
60     $ref: /schemas/types.yaml#/definitions/phandle-array
64   - compatible
65   - reg
66   - interrupts
67   - power-domains
68   - clocks
73   - |
74     #include <dt-bindings/interrupt-controller/arm-gic.h>
75     #include <dt-bindings/clock/mt8173-clk.h>
76     #include <dt-bindings/power/mt8173-power.h>
77     #include <dt-bindings/gce/mt8173-gce.h>
80         #address-cells = <2>;
81         #size-cells = <2>;
84            compatible = "mediatek,mt8173-disp-aal";
85            reg = <0 0x14015000 0 0x1000>;
87            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
89            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;