Lines Matching +full:opp +full:- +full:2
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
18 according to the required OPPs defined in the CPU OPP tables.
20 For old implementation efuses are parsed to select the correct opp table and
28 - qcom,apq8064
29 - qcom,apq8096
30 - qcom,ipq8064
31 - qcom,ipq8074
32 - qcom,msm8939
33 - qcom,msm8960
34 - qcom,msm8974
35 - qcom,msm8996
36 - qcom,qcs404
38 - compatible
41 '^opp-table(-[a-z0-9]+)?$':
43 - if:
46 const: operating-points-v2-kryo-cpu
48 $ref: /schemas/opp/opp-v2-kryo-cpu.yaml#
50 - if:
53 const: operating-points-v2-qcom-level
55 $ref: /schemas/opp/opp-v2-qcom-level.yaml#
60 - if:
65 - qcom,qcs404
73 '^cpu@[0-9a-f]+$':
77 power-domains:
80 power-domain-names:
82 - const: cpr
85 - power-domains
86 - power-domain-names
89 '^opp-table(-[a-z0-9]+)?$':
93 const: operating-points-v2-kryo-cpu
96 '^opp-?[0-9]+$':
98 - required-opps
103 - |
106 compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
107 #address-cells = <2>;
108 #size-cells = <2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
116 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 cpu-idle-states = <&CPU_SLEEP_0>;
120 next-level-cache = <&L2_0>;
121 #cooling-cells = <2>;
123 operating-points-v2 = <&cpu_opp_table>;
124 power-domains = <&cpr>;
125 power-domain-names = "cpr";
130 compatible = "arm,cortex-a53";
132 enable-method = "psci";
133 cpu-idle-states = <&CPU_SLEEP_0>;
134 next-level-cache = <&L2_0>;
135 #cooling-cells = <2>;
137 operating-points-v2 = <&cpu_opp_table>;
138 power-domains = <&cpr>;
139 power-domain-names = "cpr";
144 compatible = "arm,cortex-a53";
146 enable-method = "psci";
147 cpu-idle-states = <&CPU_SLEEP_0>;
148 next-level-cache = <&L2_0>;
149 #cooling-cells = <2>;
151 operating-points-v2 = <&cpu_opp_table>;
152 power-domains = <&cpr>;
153 power-domain-names = "cpr";
158 compatible = "arm,cortex-a53";
160 enable-method = "psci";
161 cpu-idle-states = <&CPU_SLEEP_0>;
162 next-level-cache = <&L2_0>;
163 #cooling-cells = <2>;
165 operating-points-v2 = <&cpu_opp_table>;
166 power-domains = <&cpr>;
167 power-domain-names = "cpr";
171 cpu_opp_table: opp-table-cpu {
172 compatible = "operating-points-v2-kryo-cpu";
173 opp-shared;
175 opp-1094400000 {
176 opp-hz = /bits/ 64 <1094400000>;
177 required-opps = <&cpr_opp1>;
179 opp-1248000000 {
180 opp-hz = /bits/ 64 <1248000000>;
181 required-opps = <&cpr_opp2>;
183 opp-1401600000 {
184 opp-hz = /bits/ 64 <1401600000>;
185 required-opps = <&cpr_opp3>;
189 cpr_opp_table: opp-table-cpr {
190 compatible = "operating-points-v2-qcom-level";
193 opp-level = <1>;
194 qcom,opp-fuse-level = <1>;
197 opp-level = <2>;
198 qcom,opp-fuse-level = <2>;
201 opp-level = <3>;
202 qcom,opp-fuse-level = <3>;