Lines Matching +full:gcc +full:- +full:qcm2290
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm845-cpufreq-hw
27 - qcom,sm6115-cpufreq-hw
28 - qcom,sm6350-cpufreq-hw
29 - qcom,sm8150-cpufreq-hw
30 - const: qcom,cpufreq-hw
32 - description: v2 of CPUFREQ HW (EPSS)
34 - enum:
35 - qcom,qdu1000-cpufreq-epss
36 - qcom,sa8775p-cpufreq-epss
37 - qcom,sc7280-cpufreq-epss
38 - qcom,sc8280xp-cpufreq-epss
39 - qcom,sm6375-cpufreq-epss
40 - qcom,sm8250-cpufreq-epss
41 - qcom,sm8350-cpufreq-epss
42 - qcom,sm8450-cpufreq-epss
43 - qcom,sm8550-cpufreq-epss
44 - const: qcom,cpufreq-epss
49 - description: Frequency domain 0 register region
50 - description: Frequency domain 1 register region
51 - description: Frequency domain 2 register region
52 - description: Frequency domain 3 register region
54 reg-names:
57 - const: freq-domain0
58 - const: freq-domain1
59 - const: freq-domain2
60 - const: freq-domain3
64 - description: XO Clock
65 - description: GPLL0 Clock
67 clock-names:
69 - const: xo
70 - const: alternate
76 interrupt-names:
79 - const: dcvsh-irq-0
80 - const: dcvsh-irq-1
81 - const: dcvsh-irq-2
82 - const: dcvsh-irq-3
84 '#freq-domain-cells':
87 '#clock-cells':
91 - compatible
92 - reg
93 - clocks
94 - clock-names
95 - '#freq-domain-cells'
100 - if:
105 - qcom,qcm2290-cpufreq-hw
112 reg-names:
120 interrupt-names:
123 - if:
128 - qcom,qdu1000-cpufreq-epss
129 - qcom,sc7180-cpufreq-hw
130 - qcom,sc8280xp-cpufreq-epss
131 - qcom,sdm845-cpufreq-hw
132 - qcom,sm6115-cpufreq-hw
133 - qcom,sm6350-cpufreq-hw
134 - qcom,sm6375-cpufreq-epss
141 reg-names:
149 interrupt-names:
152 - if:
157 - qcom,sc7280-cpufreq-epss
158 - qcom,sm8250-cpufreq-epss
159 - qcom,sm8350-cpufreq-epss
160 - qcom,sm8450-cpufreq-epss
161 - qcom,sm8550-cpufreq-epss
168 reg-names:
176 interrupt-names:
179 - if:
184 - qcom,sm8150-cpufreq-hw
191 reg-names:
200 interrupt-names:
205 - |
206 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
207 #include <dt-bindings/clock/qcom,rpmh.h>
209 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
212 #address-cells = <2>;
213 #size-cells = <0>;
219 enable-method = "psci";
220 next-level-cache = <&L2_0>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
223 L2_0: l2-cache {
225 cache-unified;
226 cache-level = <2>;
227 next-level-cache = <&L3_0>;
228 L3_0: l3-cache {
230 cache-unified;
231 cache-level = <3>;
240 enable-method = "psci";
241 next-level-cache = <&L2_100>;
242 qcom,freq-domain = <&cpufreq_hw 0>;
244 L2_100: l2-cache {
246 cache-unified;
247 cache-level = <2>;
248 next-level-cache = <&L3_0>;
256 enable-method = "psci";
257 next-level-cache = <&L2_200>;
258 qcom,freq-domain = <&cpufreq_hw 0>;
260 L2_200: l2-cache {
262 cache-unified;
263 cache-level = <2>;
264 next-level-cache = <&L3_0>;
272 enable-method = "psci";
273 next-level-cache = <&L2_300>;
274 qcom,freq-domain = <&cpufreq_hw 0>;
276 L2_300: l2-cache {
278 cache-unified;
279 cache-level = <2>;
280 next-level-cache = <&L3_0>;
288 enable-method = "psci";
289 next-level-cache = <&L2_400>;
290 qcom,freq-domain = <&cpufreq_hw 1>;
292 L2_400: l2-cache {
294 cache-unified;
295 cache-level = <2>;
296 next-level-cache = <&L3_0>;
304 enable-method = "psci";
305 next-level-cache = <&L2_500>;
306 qcom,freq-domain = <&cpufreq_hw 1>;
308 L2_500: l2-cache {
310 cache-unified;
311 cache-level = <2>;
312 next-level-cache = <&L3_0>;
320 enable-method = "psci";
321 next-level-cache = <&L2_600>;
322 qcom,freq-domain = <&cpufreq_hw 1>;
324 L2_600: l2-cache {
326 cache-unified;
327 cache-level = <2>;
328 next-level-cache = <&L3_0>;
336 enable-method = "psci";
337 next-level-cache = <&L2_700>;
338 qcom,freq-domain = <&cpufreq_hw 1>;
340 L2_700: l2-cache {
342 cache-unified;
343 cache-level = <2>;
344 next-level-cache = <&L3_0>;
350 #address-cells = <1>;
351 #size-cells = <1>;
354 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
356 reg-names = "freq-domain0", "freq-domain1";
358 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
359 clock-names = "xo", "alternate";
361 #freq-domain-cells = <1>;
362 #clock-cells = <1>;