bindings/cpu/idle-states.yaml

21   representing the range of dynamic idle states that a processor can enter at
23   parameters required to enter/exit specific idle states on a given processor.
57   RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
60   The platform specific suspend (or idle) states of a hart can be either
63   a non-retentive suspend state will not preserve HART registers and CSR
70   Idle states are characterized for a specific system through a set of
102     between 0 and infinite time, until a wake-up event occurs.
110   min-residency: Minimum period, including preparation and entry, for a given
113   wakeup-latency: Maximum delay between the signaling of a wake-up event and the
124   for CPUs in the system by detecting how long will it take to get a CPU out
139   worst case wake-up latency it can incur if a CPU is allowed to enter an
146   The energy consumption of a cpu when it enters a power state can be roughly
172   The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
179   min-residency is defined for a given idle state as the minimum expected
180   residency time for a state (inclusive of preparation and entry) after
185   For sake of simplicity, let's consider a system with two idle states IDLE1,
222   idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
226   shallower states in a system with multiple idle states) is defined
238   a direct child of the cpus node [1] and provides a container where the
241   On ARM systems, it is a container of processor idle states nodes. If the
297       In addition to the properties listed above, a state node may require
346           (refer to section 2 of this document for a complete description).
350           Maximum delay between the signaling of a wake-up event and the CPU
364           A string used as a descriptive name for the idle state.