Lines Matching +full:min +full:- +full:residency +full:- +full:us
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
26 2 - ARM idle states
32 - Running
33 - Idle_standby
34 - Idle_retention
35 - Sleep
36 - Off
42 wake-up capabilities, hence it is not considered in this document).
52 3 - RISC-V idle states
55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
61 retentive or non-rententive in nature. A retentive suspend state will
63 a non-retentive suspend state will not preserve HART registers and CSR
67 4 - idle-states definitions
80 |<------ entry ------->|
82 |<- exit ->|
84 |<-------- min-residency -------->|
85 |<------- wakeup-latency ------->|
92 like cache flushing. This is abortable on pending wake-up
101 IDLE: This is the actual energy-saving idle period. This may last
102 between 0 and infinite time, until a wake-up event occurs.
107 entry-latency: Worst case latency required to enter the idle state. The
108 exit-latency may be guaranteed only after entry-latency has passed.
110 min-residency: Minimum period, including preparation and entry, for a given
113 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
115 to be entry-latency + exit-latency.
119 An idle CPU requires the expected min-residency time to select the most
121 (i.e. wake-up) that causes the CPU to return to the EXEC phase.
123 An operating system scheduler may need to compute the shortest wake-up delay
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
130 (e.g. waking-up) the CPU with the shortest wake-up delay.
131 The wake-up delay must take into account the entry latency if that period
137 An OS has to reliably probe the wakeup-latency since some devices can enforce
139 worst case wake-up latency it can incur if a CPU is allowed to enter an
143 The min-residency time parameter deserves further explanation since it is
153 n | /---
154 e | /------
155 r | /------
156 g | /-----
157 y | /------
158 | ----
166 -----|-------+----------------------------------
171 The graph is split in two parts delimited by time 1ms on the X-axis.
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
175 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
179 min-residency is defined for a given idle state as the minimum expected
180 residency time for a state (inclusive of preparation and entry) after
191 | /-- IDLE1
192 e | /---
193 n | /----
194 e | /---
195 r | /-----/--------- IDLE2
196 g | /-------/---------
197 y | ------------ /---|
198 | / /---- |
199 | / /--- |
200 | / /---- |
201 | / /--- |
202 | --- |
206 ---/----------------------------+------------------------
207 |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
209 IDLE2-min-residency
211 Graph 2: idle states min-residency example
214 costs, it is clear that if the idle state residency time (i.e. time till next
215 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
227 IDLE2-min-residency and corresponds to the time when energy consumption of
234 5 - idle-states node
237 The processor idle states are defined within the idle-states node, which is
243 just supports idle_standby, an idle-states node is not required.
246 6 - References
249 [1] ARM Linux Kernel documentation - CPUs bindings
252 [2] ARM Linux Kernel documentation - PSCI bindings
261 [5] ARM Linux Kernel documentation - Booting AArch64 Linux
264 [6] RISC-V Linux Kernel documentation - CPUs bindings
267 [7] RISC-V Supervisor Binary Interface (SBI)
268 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
272 const: idle-states
274 entry-method:
278 On ARM v8 64-bit this property is required.
279 On ARM 32-bit systems this property is optional
281 This assumes that the "enable-method" property is set to "psci" in the cpu
287 "^(cpu|cluster)-":
294 SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
298 additional properties specific to the entry-method defined in the
299 idle-states node. Please refer to the entry-method bindings
305 - arm,idle-state
306 - riscv,idle-state
308 arm,psci-suspend-param:
314 (i.e. idle states node with entry-method property is set to "psci")
317 riscv,sbi-suspend-param:
320 suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
323 for RISC-V systems. For more details on the suspend_type parameter
326 local-timer-stop:
332 entry-latency-us:
336 exit-latency-us:
339 The exit-latency-us duration may be guaranteed only after
340 entry-latency-us has passed.
342 min-residency-us:
344 Minimum residency duration in microseconds, inclusive of preparation
348 wakeup-latency-us:
350 Maximum delay between the signaling of a wake-up event and the CPU
354 entry-latency-us + exit-latency-us
357 PREP phase (see diagram 1, section 2) is non-neglibigle. In such
358 systems entry-latency-us + exit-latency-us will exceed
359 wakeup-latency-us by this duration.
361 idle-state-name:
369 - compatible
370 - entry-latency-us
371 - exit-latency-us
372 - min-residency-us
377 - |
380 #size-cells = <0>;
381 #address-cells = <2>;
385 compatible = "arm,cortex-a57";
387 enable-method = "psci";
388 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
394 compatible = "arm,cortex-a57";
396 enable-method = "psci";
397 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
403 compatible = "arm,cortex-a57";
405 enable-method = "psci";
406 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
412 compatible = "arm,cortex-a57";
414 enable-method = "psci";
415 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
421 compatible = "arm,cortex-a57";
423 enable-method = "psci";
424 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
430 compatible = "arm,cortex-a57";
432 enable-method = "psci";
433 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
439 compatible = "arm,cortex-a57";
441 enable-method = "psci";
442 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
448 compatible = "arm,cortex-a57";
450 enable-method = "psci";
451 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
457 compatible = "arm,cortex-a53";
459 enable-method = "psci";
460 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
466 compatible = "arm,cortex-a53";
468 enable-method = "psci";
469 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
475 compatible = "arm,cortex-a53";
477 enable-method = "psci";
478 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
484 compatible = "arm,cortex-a53";
486 enable-method = "psci";
487 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
493 compatible = "arm,cortex-a53";
495 enable-method = "psci";
496 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
502 compatible = "arm,cortex-a53";
504 enable-method = "psci";
505 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
511 compatible = "arm,cortex-a53";
513 enable-method = "psci";
514 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
520 compatible = "arm,cortex-a53";
522 enable-method = "psci";
523 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
527 idle-states {
528 entry-method = "psci";
530 CPU_RETENTION_0_0: cpu-retention-0-0 {
531 compatible = "arm,idle-state";
532 arm,psci-suspend-param = <0x0010000>;
533 entry-latency-us = <20>;
534 exit-latency-us = <40>;
535 min-residency-us = <80>;
538 CLUSTER_RETENTION_0: cluster-retention-0 {
539 compatible = "arm,idle-state";
540 local-timer-stop;
541 arm,psci-suspend-param = <0x1010000>;
542 entry-latency-us = <50>;
543 exit-latency-us = <100>;
544 min-residency-us = <250>;
545 wakeup-latency-us = <130>;
548 CPU_SLEEP_0_0: cpu-sleep-0-0 {
549 compatible = "arm,idle-state";
550 local-timer-stop;
551 arm,psci-suspend-param = <0x0010000>;
552 entry-latency-us = <250>;
553 exit-latency-us = <500>;
554 min-residency-us = <950>;
557 CLUSTER_SLEEP_0: cluster-sleep-0 {
558 compatible = "arm,idle-state";
559 local-timer-stop;
560 arm,psci-suspend-param = <0x1010000>;
561 entry-latency-us = <600>;
562 exit-latency-us = <1100>;
563 min-residency-us = <2700>;
564 wakeup-latency-us = <1500>;
567 CPU_RETENTION_1_0: cpu-retention-1-0 {
568 compatible = "arm,idle-state";
569 arm,psci-suspend-param = <0x0010000>;
570 entry-latency-us = <20>;
571 exit-latency-us = <40>;
572 min-residency-us = <90>;
575 CLUSTER_RETENTION_1: cluster-retention-1 {
576 compatible = "arm,idle-state";
577 local-timer-stop;
578 arm,psci-suspend-param = <0x1010000>;
579 entry-latency-us = <50>;
580 exit-latency-us = <100>;
581 min-residency-us = <270>;
582 wakeup-latency-us = <100>;
585 CPU_SLEEP_1_0: cpu-sleep-1-0 {
586 compatible = "arm,idle-state";
587 local-timer-stop;
588 arm,psci-suspend-param = <0x0010000>;
589 entry-latency-us = <70>;
590 exit-latency-us = <100>;
591 min-residency-us = <300>;
592 wakeup-latency-us = <150>;
595 CLUSTER_SLEEP_1: cluster-sleep-1 {
596 compatible = "arm,idle-state";
597 local-timer-stop;
598 arm,psci-suspend-param = <0x1010000>;
599 entry-latency-us = <500>;
600 exit-latency-us = <1200>;
601 min-residency-us = <3500>;
602 wakeup-latency-us = <1300>;
607 - |
608 // Example 2 (ARM 32-bit, 8-cpu system, two clusters):
611 #size-cells = <0>;
612 #address-cells = <1>;
616 compatible = "arm,cortex-a15";
618 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
623 compatible = "arm,cortex-a15";
625 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
630 compatible = "arm,cortex-a15";
632 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
637 compatible = "arm,cortex-a15";
639 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
644 compatible = "arm,cortex-a7";
646 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
651 compatible = "arm,cortex-a7";
653 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
658 compatible = "arm,cortex-a7";
660 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
665 compatible = "arm,cortex-a7";
667 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
670 idle-states {
671 cpu_sleep_0_0: cpu-sleep-0-0 {
672 compatible = "arm,idle-state";
673 local-timer-stop;
674 entry-latency-us = <200>;
675 exit-latency-us = <100>;
676 min-residency-us = <400>;
677 wakeup-latency-us = <250>;
680 cluster_sleep_0: cluster-sleep-0 {
681 compatible = "arm,idle-state";
682 local-timer-stop;
683 entry-latency-us = <500>;
684 exit-latency-us = <1500>;
685 min-residency-us = <2500>;
686 wakeup-latency-us = <1700>;
689 cpu_sleep_1_0: cpu-sleep-1-0 {
690 compatible = "arm,idle-state";
691 local-timer-stop;
692 entry-latency-us = <300>;
693 exit-latency-us = <500>;
694 min-residency-us = <900>;
695 wakeup-latency-us = <600>;
698 cluster_sleep_1: cluster-sleep-1 {
699 compatible = "arm,idle-state";
700 local-timer-stop;
701 entry-latency-us = <800>;
702 exit-latency-us = <2000>;
703 min-residency-us = <6500>;
704 wakeup-latency-us = <2300>;
709 - |
710 // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
713 #size-cells = <0>;
714 #address-cells = <1>;
721 mmu-type = "riscv,sv48";
722 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
725 cpu_intc0: interrupt-controller {
726 #interrupt-cells = <1>;
727 compatible = "riscv,cpu-intc";
728 interrupt-controller;
737 mmu-type = "riscv,sv48";
738 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
741 cpu_intc1: interrupt-controller {
742 #interrupt-cells = <1>;
743 compatible = "riscv,cpu-intc";
744 interrupt-controller;
753 mmu-type = "riscv,sv48";
754 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
757 cpu_intc10: interrupt-controller {
758 #interrupt-cells = <1>;
759 compatible = "riscv,cpu-intc";
760 interrupt-controller;
769 mmu-type = "riscv,sv48";
770 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
773 cpu_intc11: interrupt-controller {
774 #interrupt-cells = <1>;
775 compatible = "riscv,cpu-intc";
776 interrupt-controller;
780 idle-states {
781 CPU_RET_0_0: cpu-retentive-0-0 {
782 compatible = "riscv,idle-state";
783 riscv,sbi-suspend-param = <0x10000000>;
784 entry-latency-us = <20>;
785 exit-latency-us = <40>;
786 min-residency-us = <80>;
789 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
790 compatible = "riscv,idle-state";
791 riscv,sbi-suspend-param = <0x90000000>;
792 entry-latency-us = <250>;
793 exit-latency-us = <500>;
794 min-residency-us = <950>;
797 CLUSTER_RET_0: cluster-retentive-0 {
798 compatible = "riscv,idle-state";
799 riscv,sbi-suspend-param = <0x11000000>;
800 local-timer-stop;
801 entry-latency-us = <50>;
802 exit-latency-us = <100>;
803 min-residency-us = <250>;
804 wakeup-latency-us = <130>;
807 CLUSTER_NONRET_0: cluster-nonretentive-0 {
808 compatible = "riscv,idle-state";
809 riscv,sbi-suspend-param = <0x91000000>;
810 local-timer-stop;
811 entry-latency-us = <600>;
812 exit-latency-us = <1100>;
813 min-residency-us = <2700>;
814 wakeup-latency-us = <1500>;
817 CPU_RET_1_0: cpu-retentive-1-0 {
818 compatible = "riscv,idle-state";
819 riscv,sbi-suspend-param = <0x10000010>;
820 entry-latency-us = <20>;
821 exit-latency-us = <40>;
822 min-residency-us = <80>;
825 CPU_NONRET_1_0: cpu-nonretentive-1-0 {
826 compatible = "riscv,idle-state";
827 riscv,sbi-suspend-param = <0x90000010>;
828 entry-latency-us = <250>;
829 exit-latency-us = <500>;
830 min-residency-us = <950>;
833 CLUSTER_RET_1: cluster-retentive-1 {
834 compatible = "riscv,idle-state";
835 riscv,sbi-suspend-param = <0x11000010>;
836 local-timer-stop;
837 entry-latency-us = <50>;
838 exit-latency-us = <100>;
839 min-residency-us = <250>;
840 wakeup-latency-us = <130>;
843 CLUSTER_NONRET_1: cluster-nonretentive-1 {
844 compatible = "riscv,idle-state";
845 riscv,sbi-suspend-param = <0x91000010>;
846 local-timer-stop;
847 entry-latency-us = <600>;
848 exit-latency-us = <1100>;
849 min-residency-us = <2700>;
850 wakeup-latency-us = <1500>;