bindings/clock/xlnx%2Cclocking-wizard.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
20       - xlnx,clocking-wizard
21       - xlnx,clocking-wizard-v5.2
22       - xlnx,clocking-wizard-v6.0
28   "#clock-cells":
33       - description: clock input
34       - description: axi clock
36   clock-names:
38       - const: clk_in1
39       - const: s_axi_aclk
42   xlnx,speed-grade:
46       Speed grade of the device. Higher the speed grade faster is the FPGA device.
48   xlnx,nr-outputs:
56   - compatible
57   - reg
58   - "#clock-cells"
59   - clocks
60   - clock-names
61   - xlnx,speed-grade
62   - xlnx,nr-outputs
67   - |
68     clock-controller@b0000000  {
69         compatible = "xlnx,clocking-wizard";
71         #clock-cells = <1>;
72         xlnx,speed-grade = <1>;
73         xlnx,nr-outputs = <6>;
74         clock-names = "clk_in1", "s_axi_aclk";