Lines Matching refs:output

12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
42 	The second value is the output or synthesizer index.
53   feedback divider. Must be such that the PLL output is in the valid range. For
60   temporarily stop all output clocks, don't do this if the chip is generating
67 - vddoX-supply (where X is an output index): Regulator node for VDDO for the
68   specified output. The driver selects the output VDD_SEL setting based on this
76 The child nodes list the output clocks.
79 If a child node for a clock output is not set, the configuration remains
83 - reg: number of clock output.
90 - silabs,common-mode: Manually override output common mode, see [2] for values
91 - silabs,amplitude: Manually override output amplitude, see [2] for values
92 - silabs,synth-master: boolean. If present, this output is allowed to change the
94 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
158 	/* Set output 7 to use syntesizer 3 as its parent */
161 	/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
169 	 * since output 0 is a synth-master, the synth will be automatically set
171 	 * frequency. We give control over synth 2 to this output here.