Lines Matching +full:clock +full:- +full:xxti
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos7 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
18 - "fin_pll" - PLL input clock from XXTI
21 include/dt-bindings/clock/exynos7-clk.h header.
26 - samsung,exynos7-clock-topc
27 - samsung,exynos7-clock-top0
28 - samsung,exynos7-clock-top1
29 - samsung,exynos7-clock-ccore
30 - samsung,exynos7-clock-peric0
31 - samsung,exynos7-clock-peric1
32 - samsung,exynos7-clock-peris
33 - samsung,exynos7-clock-fsys0
34 - samsung,exynos7-clock-fsys1
35 - samsung,exynos7-clock-mscl
36 - samsung,exynos7-clock-aud
42 clock-names:
46 "#clock-cells":
53 - compatible
54 - "#clock-cells"
55 - reg
58 - if:
62 const: samsung,exynos7-clock-top0
68 clock-names:
70 - const: fin_pll
71 - const: dout_sclk_bus0_pll
72 - const: dout_sclk_bus1_pll
73 - const: dout_sclk_cc_pll
74 - const: dout_sclk_mfc_pll
75 - const: dout_sclk_aud_pll
77 - clock-names
78 - clocks
80 - if:
84 const: samsung,exynos7-clock-top1
90 clock-names:
92 - const: fin_pll
93 - const: dout_sclk_bus0_pll
94 - const: dout_sclk_bus1_pll
95 - const: dout_sclk_cc_pll
96 - const: dout_sclk_mfc_pll
98 - clock-names
99 - clocks
101 - if:
105 const: samsung,exynos7-clock-ccore
111 clock-names:
113 - const: fin_pll
114 - const: dout_aclk_ccore_133
116 - clock-names
117 - clocks
119 - if:
123 const: samsung,exynos7-clock-peric0
129 clock-names:
131 - const: fin_pll
132 - const: dout_aclk_peric0_66
133 - const: sclk_uart0
135 - clock-names
136 - clocks
138 - if:
142 const: samsung,exynos7-clock-peric1
148 clock-names:
150 - const: fin_pll
151 - const: dout_aclk_peric1_66
152 - const: sclk_uart1
153 - const: sclk_uart2
154 - const: sclk_uart3
155 - const: sclk_spi0
156 - const: sclk_spi1
157 - const: sclk_spi2
158 - const: sclk_spi3
159 - const: sclk_spi4
160 - const: sclk_i2s1
161 - const: sclk_pcm1
162 - const: sclk_spdif
164 - clock-names
165 - clocks
167 - if:
171 const: samsung,exynos7-clock-peris
177 clock-names:
179 - const: fin_pll
180 - const: dout_aclk_peris_66
182 - clock-names
183 - clocks
185 - if:
189 const: samsung,exynos7-clock-fsys0
195 clock-names:
197 - const: fin_pll
198 - const: dout_aclk_fsys0_200
199 - const: dout_sclk_mmc2
201 - clock-names
202 - clocks
204 - if:
208 const: samsung,exynos7-clock-fsys1
214 clock-names:
216 - const: fin_pll
217 - const: dout_aclk_fsys1_200
218 - const: dout_sclk_mmc0
219 - const: dout_sclk_mmc1
220 - const: dout_sclk_ufsunipro20
221 - const: dout_sclk_phy_fsys1
222 - const: dout_sclk_phy_fsys1_26m
224 - clock-names
225 - clocks
227 - if:
231 const: samsung,exynos7-clock-aud
237 clock-names:
239 - const: fin_pll
240 - const: fout_aud_pll
242 - clock-names
243 - clocks
248 - |
249 #include <dt-bindings/clock/exynos7-clk.h>
251 fin_pll: clock {
252 compatible = "fixed-clock";
253 clock-output-names = "fin_pll";
254 #clock-cells = <0>;
255 clock-frequency = <24000000>;
258 clock-controller@105e0000 {
259 compatible = "samsung,exynos7-clock-top1";
261 #clock-cells = <1>;
267 clock-names = "fin_pll",