bindings/clock/qcom%2Csm8450-videocc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Taniya Das <quic_tdas@quicinc.com>
16   See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
21       - qcom,sm8450-videocc
22       - qcom,sm8550-videocc
29       - description: Board XO source
30       - description: Video AHB clock from GCC
32   power-domains:
37   required-opps:
40       A phandle to an OPP node describing required MMCX performance point.
42   '#clock-cells':
45   '#reset-cells':
48   '#power-domain-cells':
51 required:
52   - compatible
53   - reg
54   - clocks
55   - power-domains
56   - required-opps
57   - '#clock-cells'
58   - '#reset-cells'
59   - '#power-domain-cells'
64   - |
65     #include <dt-bindings/clock/qcom,gcc-sm8450.h>
66     #include <dt-bindings/clock/qcom,rpmh.h>
67     #include <dt-bindings/power/qcom,rpmhpd.h>
68     videocc: clock-controller@aaf0000 {
69       compatible = "qcom,sm8450-videocc";
73       power-domains = <&rpmhpd RPMHPD_MMCX>;
74       required-opps = <&rpmhpd_opp_low_svs>;
75       #clock-cells = <1>;
76       #reset-cells = <1>;
77       #power-domain-cells = <1>;