bindings/clock/qcom%2Cgcc-sdm845.yaml

1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Stephen Boyd <sboyd@kernel.org>
11   - Taniya Das <quic_tdas@quicinc.com>
17   See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
22       - qcom,gcc-sdm670
23       - qcom,gcc-sdm845
29   clock-names:
33   power-domains:
34     maxItems: 1
37   - compatible
40   - $ref: qcom,gcc.yaml#
41   - if:
45             const: qcom,gcc-sdm670
50             - description: Board XO source
51             - description: Board active XO source
52             - description: Sleep clock source
53         clock-names:
55             - const: bi_tcxo
56             - const: bi_tcxo_ao
57             - const: sleep_clk
59   - if:
63             const: qcom,gcc-sdm845
68             - description: Board XO source
69             - description: Board active XO source
70             - description: Sleep clock source
71             - description: PCIE 0 Pipe clock source
72             - description: PCIE 1 Pipe clock source
73         clock-names:
75             - const: bi_tcxo
76             - const: bi_tcxo_ao
77             - const: sleep_clk
78             - const: pcie_0_pipe_clk
79             - const: pcie_1_pipe_clk
85   - |
86     #include <dt-bindings/clock/qcom,rpmh.h>
87     clock-controller@100000 {
88       compatible = "qcom,gcc-sdm845";
95       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
96       #clock-cells = <1>;
97       #reset-cells = <1>;
98       #power-domain-cells = <1>;