bindings/clock/pistachio-clock.txt

6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1.  The single cell is the clock identifier.
27   See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
31   top-level general control.
34 	clk_core: clock-controller@18144000 {
35 		compatible = "img,pistachio-clk";
39 		clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
41 		#clock-cells = <1>;
45 ----------------------------
48 peripherals.  The peripheral system clock ("periph_sys") generated by the core
52 - compatible: Must be "img,pistachio-periph-clk".
53 - reg: Must contain the base address and length of the peripheral clock
55 - #clock-cells: Must be 1.  The single cell is the clock identifier.
56   See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
57 - clocks: Must contain an entry for each clock in clock-names.
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
62 	clk_periph: clock-controller@18144800 {
63 		compatible = "img,pistachio-clk-periph";
66 		clock-names = "periph_sys";
68 		#clock-cells = <1>;
72 ---------------------------
74 The peripheral general control block generates system interface clocks and
76 control registers.  The system clock ("sys") generated by the peripheral clock
77 controller is the input clock to the system clock controller.
80 - compatible: Must include "img,pistachio-periph-cr" and "syscon".
81 - reg: Must contain the base address and length of the peripheral general
83 - #clock-cells: Must be 1.  The single cell is the clock identifier.
84   See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
85 - clocks: Must contain an entry for each clock in clock-names.
86 - clock-names: Must include "sys", the system clock generated by the peripheral
91 		compatible = "img,pistachio-cr-periph", "syscon";
94 		clock-names = "sys";
96 		#clock-cells = <1>;
99 Top-level general control:
100 --------------------------
102 The top-level general control block contains miscellaneous control registers and
106 - compatible: Must include "img,pistachio-cr-top" and "syscon".
107 - reg: Must contain the base address and length of the top-level
109 - clocks: Must contain an entry for each clock in clock-names.
110 - clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
112 - #clock-cells: Must be 1.  The single cell is the clock identifier.
113   See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
117 		compatible = "img,pistachio-cr-top", "syscon";
120 		clock-names = "audio_clk_in", "enet_clk_in";
122 		#clock-cells = <1>;