bindings/clock/imx7ulp-scg-clock.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10   - A.s. Dong <aisheng.dong@nxp.com>
13   i.MX7ULP Clock functions are under joint control of the System
19   domains, such as the System Oscillator clock, the Slow IRC (SIRC),
21   management are separated and contained within each domain.
23   M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24   A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
28   The System Clock Generation (SCG) is responsible for clock generation
31   processor, system, peripheral bus and external memory interface clocks,
37   See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
42     const: fsl,imx7ulp-scg1
47   '#clock-cells':
52       - description: rtc osc
53       - description: system osc
54       - description: slow internal reference clock
55       - description: fast internal reference clock
56       - description: usb PLL
58   clock-names:
60       - const: rosc
61       - const: sosc
62       - const: sirc
63       - const: firc
64       - const: upll
67   - compatible
68   - reg
69   - '#clock-cells'
70   - clocks
71   - clock-names
76   - |
77     #include <dt-bindings/clock/imx7ulp-clock.h>
78     #include <dt-bindings/interrupt-controller/arm-gic.h>
80     clock-controller@403e0000 {
81         compatible = "fsl,imx7ulp-scg1";
85         clock-names = "rosc", "sosc", "sirc",
87         #clock-cells = <1>;