bindings/clock/adi%2Caxi-clkgen.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10   - Lars-Peter Clausen <lars@metafoo.de>
11   - Michael Hennerich <michael.hennerich@analog.com>
22       - adi,axi-clkgen-2.00.a
23       - adi,zynqmp-axi-clkgen-2.00.a
30       clock is the AXI bus clock that needs to be enabled so we can access the
32     minItems: 2
35   clock-names:
37       - items:
38           - const: clkin1
39           - const: s_axi_aclk
40       - items:
41           - const: clkin1
42           - const: clkin2
43           - const: s_axi_aclk
45   '#clock-cells':
52   - compatible
53   - reg
54   - clocks
55   - clock-names
56   - '#clock-cells'
61   - |
62     clock-controller@ff000000 {
63       compatible = "adi,axi-clkgen-2.00.a";
64       #clock-cells = <0>;
67       clock-names = "clkin1", "s_axi_aclk";