bindings/cache/qcom%2Cllcc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <andersson@kernel.org>
13   LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
23       - qcom,sc7180-llcc
24       - qcom,sc7280-llcc
25       - qcom,sc8180x-llcc
26       - qcom,sc8280xp-llcc
27       - qcom,sdm845-llcc
28       - qcom,sm6350-llcc
29       - qcom,sm7150-llcc
30       - qcom,sm8150-llcc
31       - qcom,sm8250-llcc
32       - qcom,sm8350-llcc
33       - qcom,sm8450-llcc
34       - qcom,sm8550-llcc
40   reg-names:
48   - compatible
49   - reg
50   - reg-names
53   - if:
58               - qcom,sc7180-llcc
59               - qcom,sm6350-llcc
64             - description: LLCC0 base register region
65             - description: LLCC broadcast base register region
66         reg-names:
68             - const: llcc0_base
69             - const: llcc_broadcast_base
71   - if:
76               - qcom,sc7280-llcc
81             - description: LLCC0 base register region
82             - description: LLCC1 base register region
83             - description: LLCC broadcast base register region
84         reg-names:
86             - const: llcc0_base
87             - const: llcc1_base
88             - const: llcc_broadcast_base
90   - if:
95               - qcom,sc8180x-llcc
96               - qcom,sc8280xp-llcc
101             - description: LLCC0 base register region
102             - description: LLCC1 base register region
103             - description: LLCC2 base register region
104             - description: LLCC3 base register region
105             - description: LLCC4 base register region
106             - description: LLCC5 base register region
107             - description: LLCC6 base register region
108             - description: LLCC7 base register region
109             - description: LLCC broadcast base register region
110         reg-names:
112             - const: llcc0_base
113             - const: llcc1_base
114             - const: llcc2_base
115             - const: llcc3_base
116             - const: llcc4_base
117             - const: llcc5_base
118             - const: llcc6_base
119             - const: llcc7_base
120             - const: llcc_broadcast_base
122   - if:
127               - qcom,sdm845-llcc
128               - qcom,sm8150-llcc
129               - qcom,sm8250-llcc
130               - qcom,sm8350-llcc
131               - qcom,sm8450-llcc
132               - qcom,sm8550-llcc
137             - description: LLCC0 base register region
138             - description: LLCC1 base register region
139             - description: LLCC2 base register region
140             - description: LLCC3 base register region
141             - description: LLCC broadcast base register region
142         reg-names:
144             - const: llcc0_base
145             - const: llcc1_base
146             - const: llcc2_base
147             - const: llcc3_base
148             - const: llcc_broadcast_base
153   - |
154     #include <dt-bindings/interrupt-controller/arm-gic.h>
157         #address-cells = <2>;
158         #size-cells = <2>;
160         system-cache-controller@1100000 {
161             compatible = "qcom,sdm845-llcc";
165             reg-names = "llcc0_base", "llcc1_base", "llcc2_base",