bindings/cache/l2c2x0.yaml

4 $id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
14   PL220/PL310 and variants) based level 2 cache controller. All these various
15   implementations of the L2 cache controller have compatible programming
16   models (Note 1). Some of the properties that are just prefixed "cache-*" are
22     cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28   - $ref: /schemas/cache-controller.yaml#
34           - arm,pl310-cache
35           - arm,l220-cache
36           - arm,l210-cache
37             # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38           - bcm,bcm11351-a2-pl310-cache
41             # cache controller
42           - brcm,bcm11351-a2-pl310-cache
44             # compatible with the ARM one, with system cache mode (meaning
47           - marvell,aurora-system-cache
49             # compatible with the ARM one with outer cache mode.
50           - marvell,aurora-outer-cache
52            # Marvell Tauros3 cache controller, compatible
53            # with arm,pl310-cache controller.
54           - const: marvell,tauros3-cache
55           - const: arm,pl310-cache
57   cache-level:
60   cache-unified: true
61   cache-size: true
62   cache-sets: true
63   cache-block-size: true
64   cache-line-size: true
109       I/O coherent mode. Valid only when the arm,pl310-cache compatible
118   cache-id-part:
119     description: cache id part number to be used if it is not present
157     description: The default behavior of the L220 or PL310 cache
166     description: enable parity checking on the L2 cache (L220 or PL310).
170     description: disable parity checking on the L2 cache (L220 or PL310).
174     description: enable ECC protection on the L2 cache
178     description: disable the outer sync operation on the L2 cache.
179       Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
224   - cache-unified
231     cache-controller@fff12000 {
232         compatible = "arm,pl310-cache";
237         cache-unified;
238         cache-level = <2>;