arm/msm/qcom%2Cidle-state.txt

1 QCOM Idle States for cpuidle driver
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
16 trigger to execute the SPM state machine. The SPM state machine waits for the
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
19 the SPM state machine out of its wait, the next step is to ensure that the
21 execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
22 driver and is not defined in the DT. The SPM state machine should be
23 configured to execute this state by default and after executing every other
24 state below.
26 Retention: Retention is a low power state where the core is clock gated and
31 state. Retention may have a slightly higher latency than Standby.
34 between the time it enters idle and the next known wake up. SPC mode is used
35 to indicate a core entering a power down state without consulting any other
37 sequence for this idle state is programmed to power down the supply to the
39 system state including cache hierarchy is ready before allowing core to
42 kernel. Entering a power down state for the cpu, needs to be done by trapping
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
47 Power Collapse: This state is similar to the SPC mode, but distinguishes
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
51 voltages reduced, provided all cpus enter this state.  Since the span of low
52 power modes possible at this state is vast, the exit latency and the residency
54 this essentially is cpu power down. The SPM in this state also may handshake
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
61 The devicetree representation of the idle state should be -
65 - compatible: Must be one of -
66 			"qcom,idle-state-ret",
67 			"qcom,idle-state-spc",
68 			"qcom,idle-state-pc",
69 		and "arm,idle-state".
75 	idle-states {
77 			compatible = "qcom,idle-state-spc", "arm,idle-state";
78 			entry-latency-us = <150>;
79 			exit-latency-us = <200>;
80 			min-residency-us = <2000>;
84 [1]. Documentation/devicetree/bindings/cpu/idle-states.yaml