Lines Matching +full:mt8195 +full:- +full:ipesys
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8195
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
26 - enum:
27 - mediatek,mt8195-scp_adsp
28 - mediatek,mt8195-imp_iic_wrap_s
29 - mediatek,mt8195-imp_iic_wrap_w
30 - mediatek,mt8195-mfgcfg
31 - mediatek,mt8195-wpesys
32 - mediatek,mt8195-wpesys_vpp0
33 - mediatek,mt8195-wpesys_vpp1
34 - mediatek,mt8195-imgsys
35 - mediatek,mt8195-imgsys1_dip_top
36 - mediatek,mt8195-imgsys1_dip_nr
37 - mediatek,mt8195-imgsys1_wpe
38 - mediatek,mt8195-ipesys
39 - mediatek,mt8195-camsys
40 - mediatek,mt8195-camsys_rawa
41 - mediatek,mt8195-camsys_yuva
42 - mediatek,mt8195-camsys_rawb
43 - mediatek,mt8195-camsys_yuvb
44 - mediatek,mt8195-camsys_mraw
45 - mediatek,mt8195-ccusys
46 - mediatek,mt8195-vdecsys_soc
47 - mediatek,mt8195-vdecsys
48 - mediatek,mt8195-vdecsys_core1
49 - mediatek,mt8195-vencsys
50 - mediatek,mt8195-vencsys_core1
51 - mediatek,mt8195-apusys_pll
55 '#clock-cells':
59 - compatible
60 - reg
65 - |
66 scp_adsp: clock-controller@10720000 {
67 compatible = "mediatek,mt8195-scp_adsp";
69 #clock-cells = <1>;
72 - |
73 imp_iic_wrap_s: clock-controller@11d03000 {
74 compatible = "mediatek,mt8195-imp_iic_wrap_s";
76 #clock-cells = <1>;
79 - |
80 imp_iic_wrap_w: clock-controller@11e05000 {
81 compatible = "mediatek,mt8195-imp_iic_wrap_w";
83 #clock-cells = <1>;
86 - |
87 mfgcfg: clock-controller@13fbf000 {
88 compatible = "mediatek,mt8195-mfgcfg";
90 #clock-cells = <1>;
93 - |
94 wpesys: clock-controller@14e00000 {
95 compatible = "mediatek,mt8195-wpesys";
97 #clock-cells = <1>;
100 - |
101 wpesys_vpp0: clock-controller@14e02000 {
102 compatible = "mediatek,mt8195-wpesys_vpp0";
104 #clock-cells = <1>;
107 - |
108 wpesys_vpp1: clock-controller@14e03000 {
109 compatible = "mediatek,mt8195-wpesys_vpp1";
111 #clock-cells = <1>;
114 - |
115 imgsys: clock-controller@15000000 {
116 compatible = "mediatek,mt8195-imgsys";
118 #clock-cells = <1>;
121 - |
122 imgsys1_dip_top: clock-controller@15110000 {
123 compatible = "mediatek,mt8195-imgsys1_dip_top";
125 #clock-cells = <1>;
128 - |
129 imgsys1_dip_nr: clock-controller@15130000 {
130 compatible = "mediatek,mt8195-imgsys1_dip_nr";
132 #clock-cells = <1>;
135 - |
136 imgsys1_wpe: clock-controller@15220000 {
137 compatible = "mediatek,mt8195-imgsys1_wpe";
139 #clock-cells = <1>;
142 - |
143 ipesys: clock-controller@15330000 {
144 compatible = "mediatek,mt8195-ipesys";
146 #clock-cells = <1>;
149 - |
150 camsys: clock-controller@16000000 {
151 compatible = "mediatek,mt8195-camsys";
153 #clock-cells = <1>;
156 - |
157 camsys_rawa: clock-controller@1604f000 {
158 compatible = "mediatek,mt8195-camsys_rawa";
160 #clock-cells = <1>;
163 - |
164 camsys_yuva: clock-controller@1606f000 {
165 compatible = "mediatek,mt8195-camsys_yuva";
167 #clock-cells = <1>;
170 - |
171 camsys_rawb: clock-controller@1608f000 {
172 compatible = "mediatek,mt8195-camsys_rawb";
174 #clock-cells = <1>;
177 - |
178 camsys_yuvb: clock-controller@160af000 {
179 compatible = "mediatek,mt8195-camsys_yuvb";
181 #clock-cells = <1>;
184 - |
185 camsys_mraw: clock-controller@16140000 {
186 compatible = "mediatek,mt8195-camsys_mraw";
188 #clock-cells = <1>;
191 - |
192 ccusys: clock-controller@17200000 {
193 compatible = "mediatek,mt8195-ccusys";
195 #clock-cells = <1>;
198 - |
199 vdecsys_soc: clock-controller@1800f000 {
200 compatible = "mediatek,mt8195-vdecsys_soc";
202 #clock-cells = <1>;
205 - |
206 vdecsys: clock-controller@1802f000 {
207 compatible = "mediatek,mt8195-vdecsys";
209 #clock-cells = <1>;
212 - |
213 vdecsys_core1: clock-controller@1803f000 {
214 compatible = "mediatek,mt8195-vdecsys_core1";
216 #clock-cells = <1>;
219 - |
220 vencsys: clock-controller@1a000000 {
221 compatible = "mediatek,mt8195-vencsys";
223 #clock-cells = <1>;
226 - |
227 vencsys_core1: clock-controller@1b000000 {
228 compatible = "mediatek,mt8195-vencsys_core1";
230 #clock-cells = <1>;
233 - |
234 apusys_pll: clock-controller@190f3000 {
235 compatible = "mediatek,mt8195-apusys_pll";
237 #clock-cells = <1>;