Lines Matching refs:a
27 SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
30 controller (MEMC). This BIU block offers a feature called Write Pairing which
31 consists in collapsing two adjacent cache lines into a single (bursted) write
82 o a phandle to the "hif_cpubiuctrl" syscon node
89 o a phandle to the "hif_continuation" syscon node
110 o a phandle to "sun_top_ctrl"
146 A Broadcom STB SoC typically has a number of independent memory controllers,
149 describing these controllers as a parent "memory controllers" block, which
151 associated with a number of hardware register resources (e.g., its PHY). See
156 Represents a single memory controller instance.
190 See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a