arm/bcm/brcm%2Cbrcmstb.txt

2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7     - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11     #address-cells = <2>;
12     #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19     - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20     - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 		  "brcm,brcmstb-cpu-biu-ctrl",
23     - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
25 cpu-biu-ctrl node
26 -------------------
27 SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
28 specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
29 complex to the different Memory Controller Ports (MCP), one per memory
30 controller (MEMC). This BIU block offers a feature called Write Pairing which
32 transaction towards the memory controller (MEMC) to maximize write bandwidth.
36     - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
40     - brcm,write-pairing:
42 	supports write-pairing.
46         #address-cells = <1>;
47         #size-cells = <1>;
48         compatible = "simple-bus";
52             compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
57             compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
59             brcm,write-pairing;
63             compatible = "brcm,bcm7445-hif-continuation", "syscon";
71 -------
74     - compatible
75         The string "brcm,brcmstb-smpboot".
77     - syscon-cpu
79         of certain CPU power-on registers.
83             o offset to the base CPU power zone register
84             o offset to the base CPU reset register
86     - syscon-cont
87         A phandle pointing to the syscon node which describes the CPU boot
93         compatible = "brcm,brcmstb-smpboot";
94         syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
95         syscon-cont = <&hif_continuation>;
99 -------
102     - compatible
103         The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
104         the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
107     - syscon
116         compatible = "brcm,brcmstb-reboot";
122 Power management
123 ----------------
125 For power management (particularly, S2/S3/S5 system suspend), the following SoC
128 = Always-On control block (AON CTRL)
130 This hardware provides control registers for the "always-on" (even in low-power
131 modes) hardware, such as the Power Management State Machine (PMSM).
134 - compatible     : should contain "brcm,brcmstb-aon-ctrl"
135 - reg            : the register start and length for the AON CTRL block
139 aon-ctrl@410000 {
140 	compatible = "brcm,brcmstb-aon-ctrl";
150 contains N sub-nodes (one for each controller in the system), each of which is
154 == MEMC (MEMory Controller)
156 Represents a single memory controller instance.
159 - compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
165 Control registers for this memory controller's DDR PHY.
168 - compatible     : should contain one of these
169 	"brcm,brcmstb-ddr-phy-v71.1"
170 	"brcm,brcmstb-ddr-phy-v72.0"
171 	"brcm,brcmstb-ddr-phy-v225.1"
172 	"brcm,brcmstb-ddr-phy-v240.1"
173 	"brcm,brcmstb-ddr-phy-v240.2"
175 - reg            : the DDR PHY register range
179 Control registers for this memory controller's DDR SHIMPHY.
182 - compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
183 - reg            : the DDR SHIMPHY register range
187 Sequencer DRAM parameters and control registers. Used for Self-Refresh
188 Power-Down (SRPD), among other things.
190 See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
197 	compatible = "simple-bus";
200 		compatible = "brcm,brcmstb-memc", "simple-bus";
203 		ddr-phy@f1106000 {
204 			compatible = "brcm,brcmstb-ddr-phy-v240.1";
209 			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
213 		memc-ddr@f1102000 {
215 			compatible = "brcm,brcmstb-memc-ddr";
220 		compatible = "brcm,brcmstb-memc", "simple-bus";
223 		ddr-phy@f1186000 {
224 			compatible = "brcm,brcmstb-ddr-phy-v240.1";
229 			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
233 		memc-ddr@f1182000 {
235 			compatible = "brcm,brcmstb-memc-ddr";
240 		compatible = "brcm,brcmstb-memc", "simple-bus";
243 		ddr-phy@f1206000 {
244 			compatible = "brcm,brcmstb-ddr-phy-v240.1";
249 			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
253 		memc-ddr@f1202000 {
255 			compatible = "brcm,brcmstb-memc-ddr";