arch/x86/tlb.rst

1 .. SPDX-License-Identifier: GPL-2.0
10  1. Flush the entire TLB with a two-instruction sequence.  This is
14  2. Use the invlpg instruction to invalidate a single page at a
32  4. The microarchitecture.  The TLB has become a multi-level
34     expensive relative to single-page flushes.
53 Despite the fact that a single individual flush on x86 is
67   perf stat -e
68     cpu/event=0x8,umask=0x84,name=dtlb_load_misses_walk_duration/,
69     cpu/event=0x8,umask=0x82,name=dtlb_load_misses_walk_completed/,
70     cpu/event=0x49,umask=0x4,name=dtlb_store_misses_walk_duration/,
71     cpu/event=0x49,umask=0x2,name=dtlb_store_misses_walk_completed/,
72     cpu/event=0x85,umask=0x4,name=itlb_misses_walk_duration/,
73     cpu/event=0x85,umask=0x2,name=itlb_misses_walk_completed/
75 That works on an IvyBridge-era CPU (i5-3320M).  Different CPUs
76 may have differently-named counters, but they should at least
77 be there in some form.  You can use pmu-tools 'ocperf list'
78 (https://github.com/andikleen/pmu-tools) to find the right
79 counters for a given CPU.