arch/x86/iommu.rst

7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf
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21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
26 - IVHD - AMD I/O Virtualization Hardware Definition
33 reserved in the e820 map. When we turn on DMA translation, DMA to those
41 The architecture defines an ACPI-compatible data structure called an I/O
43 related to I/O virtualization to system software.  The IVRS describes the
49 - IOMMUs present in the platform including their capabilities and proper configuration
50 - System I/O topology relevant to each IOMMU
51 - Peripheral devices that cannot be otherwise enumerated
52 - Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are generally exc…
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58 that needs to perform DMA. Once DMA is completed and mapping is no longer
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74 Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
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123 	PCI-DMA: Using DMAR IOMMU
130 	DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
132 	DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
143 	iommu: DMA domain TLB invalidation policy: lazy mode
150 	AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000]
151 	AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000]