arch/mips/ingenic-tcu.rst

1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15   (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16   64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21     - The watchdog and OST hardware blocks also feature a TCSR register with the same
23     - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
24       OST clocks.
26 - Each TCU channel works in one of two modes:
28     - mode TCU1: channels cannot work in sleep mode, but are easier to
30     - mode TCU2: channels can work in sleep mode, but the operation is a bit
33 - The mode of each TCU channel depends on the SoC used:
35     - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
37     - On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
38     - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
41 - Each channel can generate an interrupt. Some channels share an interrupt
44     - on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
45       own interrupt line; channels 2-7 share the last interrupt line.
46     - On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
47       interrupt line; the OST uses the last interrupt line.
48     - on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
49       channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
50       the OST uses the last interrupt line.
59 interrupts   drivers/irqchip/irq-ingenic-tcu.c
60 timers       drivers/clocksource/ingenic-timer.c
61 OST          drivers/clocksource/ingenic-ost.c
62 PWM          drivers/pwm/pwm-jz4740.c