arch/arm64/sme.rst

21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
67 * Whenever ZA register values are exchanged in memory between userspace and
79 controls the size of the streaming mode SVE vectors and the ZA matrix array.
80 The ZA matrix is square with each side having as many bytes as a streaming
97 * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
98   ZA matrix and ZTn (if present) are preserved.
103 * None of the SVE registers, ZA or ZTn are used to pass arguments to
118 * Signal handlers are invoked with streaming mode and ZA disabled.
123 * A new signal frame record za_context encodes the ZA register contents on
126 * The signal frame record for ZA always contains basic metadata, in particular
129 * The ZA matrix may or may not be included in the record, depending on
130   the value of PSTATE.ZA.  The registers are present if and only if:
132   in which case PSTATE.ZA == 1.
141 * If the ZA context is too big to fit in sigcontext.__reserved[], then extra
146 * If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
162   then ZA is disabled.
165   PSTATE.ZA is set to 1 and ZA is populated with the specified data.
171 * If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a
237     * Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all
244     * Changing the vector length causes PSTATE.ZA and PSTATE.SM to be cleared.
278 * A new regset NT_ARM_ZA is defined for ZA state for access to ZA state via
328   case the vector length and flags are changed and PSTATE.ZA is set to 0
330   then PSTATE.ZA will be set to 1.
345 * When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0.
347 * Writes to NT_ARM_ZT will set PSTATE.ZA to 1.
429 * A new vector length controlling the size of ZA and the Z registers when in
436 * A new ZA matrix register.  This is a square matrix of SVLxSVL bits.  Most
437   operations on ZA require that streaming mode be enabled but ZA can be
441   ZA only when it is actively being used.
444   register which is accessible when PSTATE.ZA is set, as ZA itself is.
449   * PSTATE.ZA, if this is 1 then the ZA matrix is accessible and has valid
450     data while if it is 0 then ZA can not be accessed.  When PSTATE.ZA is
451     changed from 0 to 1 all bits in ZA are cleared.