Lines Matching full:transfer

30   without the ability to generate convenient burst transfer ensuring the best
54   the STM32 DMA transfer.
58   channel is null. The channel transfer complete of the last node is the end of
59   transfer, unless first and last nodes are linked to each other, in such a
60   case, the linked-list loops on to create a circular MDMA transfer.
64   resources and bus congestion. Transfer Complete signal of STM32 DMA channel
65   can triggers STM32 MDMA transfer. STM32 MDMA can clear the request generated
73     | channels     | channels       | Transfer  | request    |
133   * the address of the STM32 DMA register to clear the Transfer Complete
135   * the mask of the Transfer Complete interrupt flag of the STM32 DMA channel.
156     If the SRAM period is greater than the expected DMA transfer, then STM32 DMA
197     destination address increment, block transfer with 128 bytes per single
198     transfer
207     Transfer Complete flag passed through
217     STM32 DMA transfer (where memory address targets now the SRAM buffer instead
218     of DDR buffer) and one for STM32 MDMA transfer (where memory address targets
294     the memory address (depending on the transfer direction) must point on your
302     channel Transfer Complete flag mask.
306     (depending on the transfer direction) must point on your SRAM buffer, and
352     or, depending on the transfer direction, either the original DDR buffer (in
359     descriptor you want a callback to be called at the end of the transfer
362     the overal transfer:
371   As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
375   transfer or the period completion.
379   it. STM32 MDMA channel will be stopped by HW in case of sg transfer, but not
380   in case of cyclic transfer. You can terminate it whatever the kind of transfer.
389   A trick could be pausing the STM32 DMA channel (that will raise a Transfer
393   "removed" from the sg or the cyclic transfer.