Documentation/admin-guide/ras.rst

64 example, a part of the memory that it is not currently allocated.
80   like a CPU in power down state or an unused memory bank, the system may
102 Typically, it is very complex for memory, as modern CPUs interlace memory
103 from different memory modules, in order to provide a better performance. The
104 DMI BIOS usually have a list of memory module labels, with can be obtained
121 On the above example, a DDR4 SO-DIMM memory module is located at the
122 system's memory labeled as "BANK 0", as given by the *bank locator* field.
124 *data width*. It means that such memory module doesn't have error
127 Unfortunately, not all systems use the same field to specify the memory
146 There, the DDR3 RDIMM memory module is located at the system's memory labeled
148 memory module has 64 bits of *data width* and 72 bits of *total width*. So,
150 Such kind of memory is called Error-correcting code memory (ECC memory).
156 ECC memory
159 As mentioned in the previous section, ECC memory has extra bits to be
160 used for error correction. In the above example, a memory module has
165 So, when the cpu requests the memory controller to write a word with
166 *data width*, the memory controller calculates the *syndrome* in real time,
169 on the memory modules.
175 The memory controller also looks at the *syndrome* in order to check if
181 at the memory controller and can be accessed by reading such registers,
186 .. [#f1] Please notice that several memory controllers allow operation on a  argument
187   mode called "Lock-Step", where it groups two memory modules together,
190   that, when an error happens, there's no way to know what memory module is
191   to blame. So, it has to blame both memory modules.
193 .. [#f2] Some memory controllers also allow using memory in mirror mode.  argument
194   On such mode, the same data is written to two memory modules. At read,
195   the system checks both memory modules, in order to check if both provide
197   way to know what memory module is to blame. So, it has to blame both
198   memory modules (or 4 memory modules, if the system is also on Lock-step
235 However, preventive maintenance and proactive part replacement of memory
245 This new device type allows for non-memory type of ECC hardware detectors
305 loads both the ``amd76x_edac.ko`` memory controller module and the
318 	mc	memory controller(s) system
327 Each ``mc`` device controls a set of memory modules [#f4]_. These modules
332   used to refer to a memory module, although there are other memory
334   specification (Version 2.7) defines a memory module in the Common
337   "dimm" is used for all memory modules, even when they use a
342 a given motherboard, memory controller and memory module characteristics.
345 data transfers to/from the CPU from/to memory. Some newer chipsets allow
346 for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory
368 for memory DIMMs:
380 which the memory DIMM is placed. Thus, when 1 DIMM is placed in each
388 repeats itself for csrow2 and csrow3. Also note that some memory
389 controllers don't have any logic to identify the memory module, see
394 ``/sys/devices/system/edac/mc``, each memory controller will be
428 this ``X`` instance of the memory controllers.
492 this ``X`` memory module:
494 - ``size`` - Total memory managed by this csrow attribute file
496 	This attribute file displays, in count of megabytes, the memory
531 - ``dimm_label`` - memory module label control file
545 - ``dimm_location`` - location of the memory module
548 	memory controller identifies the location of a memory module.
549 	Depending on the type of memory and memory controller, it
552 		- *csrow* and *channel* - used when the memory controller
554 		- *branch*, *channel*, *slot* - typically used on FB-DIMM memory
560 	This attribute file will display what type of memory is currently
561 	on this csrow. Normally, either buffered or unbuffered memory.
567 .. [#f5] On some systems, the memory controller doesn't have any logic
568 …to identify the memory module. On such systems, the directory is called ``rankX`` and works on a s…
569   On modern Intel memory controllers, the memory controller identifies the
570   memory modules directly. On such systems, the directory is called ``dimmX``.
606 - ``size_mb`` - Total memory managed by this csrow attribute file
608 	This attribute file displays, in count of megabytes, the memory
614 	This attribute file will display what type of memory is currently
615 	on this csrow. Normally, either buffered or unbuffered memory.
712 	| The memory controller                 | MC0         |
736 Both UEs and CEs with no info will lack all but memory controller, error
985 On older Intel architectures, the memory controller was part of the North
987 newer Intel architectures integrated an enhanced version of the memory
990 This chapter will cover the differences of the enhanced memory controllers
996    The Xeon E7 processor families use a separate chip for the memory
1031    Each QPI is exported as a different memory controller.
1036    For injecting a memory error, there are some sysfs nodes, under
1044          rank = the memory rank;
1108 3) Corrected Error memory register counters
1110    Those newer MCs have some registers to count memory errors. The driver
1131    So, in this memory mapping::