admin-guide/perf/hisi-pmu.rst

10 The HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
12 called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
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28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
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53   $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
54   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 1. L3C PMU supports filtering by core/thread within the cluster which can be
62   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
64 This will only count the operations from core/thread 0 and 1 in this cluster.
70 3'b111 represents atomic non-store operations, other values are reserved::
72   $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
74 This will only count the read operations in this cluster.
79 - 5'b00001: comes from L3C in this die;
80 - 5'b01000: comes from L3C in the cross-die;
81 - 5'b01001: comes from L3C which is in another socket;
82 - 5'b01110: comes from the local DDR;
83 - 5'b01111: comes from the cross-die DDR;
84 - 5'b10000: comes from cross-socket DDR;
87 cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
90   $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
96 SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
97 CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
99 - 5'b00000: I/O_MGMT_ICL;
100 - 5'b00001: Network_ICL;
101 - 5'b00011: HAC_ICL;
102 - 5'b10000: PCIe_ICL;
107 - 2'b11: count the events which sent to the uring_ext (MATA) channel;
108 - 2'b01: is the same as 2'b11;
109 - 2'b10: count the events which sent to the uring (non-MATA) channel;
110 - 2'b00: default value, count the events which sent to the both uring and