Lines Matching +full:controller +full:- +full:specific
12 #include <libcper/cper-utils.h>
13 #include <libcper/sections/cper-section-pcie.h>
23 // Base Class 00h - Legacy devices
25 "All currently implemented devices except VGA-compatible devices" },
26 { 0x00, 0x01, 0x00, "VGA-compatible device" },
28 // Base Class 01h - Mass storage controllers
29 { 0x01, 0x00, 0x00, "SCSI controller - vendor-specific interface" },
31 "SCSI storage device - SCSI over PCI Express (SOP) with PQI" },
33 "SCSI controller - SCSI over PCI Express (SOP) with PQI" },
35 "SCSI storage device and SCSI controller - SOP with PQI" },
37 "SCSI storage device - SOP with NVM Express interface" },
38 { 0x01, 0x01, ANYP, "IDE controller" },
40 "Floppy disk controller - vendor-specific interface" },
41 { 0x01, 0x03, 0x00, "IPI bus controller - vendor-specific interface" },
42 { 0x01, 0x04, 0x00, "RAID controller - vendor-specific interface" },
44 "ATA controller with ADMA interface - single stepping" },
46 "ATA controller with ADMA interface - continuous operation" },
48 "Serial ATA controller - vendor-specific interface" },
49 { 0x01, 0x06, 0x01, "Serial ATA controller - AHCI interface" },
52 "Serial Attached SCSI (SAS) controller - vendor specific interface" },
54 "Non-volatile memory subsystem - vendor-specific interface" },
56 "Non-volatile memory subsystem - NVMHCI interface" },
57 { 0x01, 0x08, 0x02, "NVM Express (NVMe) I/O controller" },
58 { 0x01, 0x08, 0x03, "NVM Express (NVMe) administrative controller" },
60 "Universal Flash Storage (UFS) controller - vendor specific interface" },
62 "Universal Flash Storage (UFS) controller - UFSHCI" },
64 "Other mass storage controller - vendor-specific interface" },
66 // Base Class 02h - Network controllers
67 { 0x02, 0x00, 0x00, "Ethernet controller" },
69 "Ethernet Controller with IDPF compliant Interface" },
70 { 0x02, 0x01, 0x00, "Token Ring controller" },
71 { 0x02, 0x02, 0x00, "FDDI controller" },
72 { 0x02, 0x03, 0x00, "ATM controller" },
73 { 0x02, 0x04, 0x00, "ISDN controller" },
74 { 0x02, 0x05, 0x00, "WorldFip controller" },
76 { 0x02, 0x07, 0x00, "InfiniBand Controller" },
77 { 0x02, 0x08, 0x00, "Host fabric controller - vendor-specific" },
78 { 0x02, 0x80, 0x00, "Other network controller" },
80 // Base Class 03h - Display controllers
81 { 0x03, 0x00, 0x00, "VGA-compatible controller" },
82 { 0x03, 0x00, 0x01, "8514-compatible controller" },
83 { 0x03, 0x01, 0x00, "XGA controller" },
84 { 0x03, 0x02, 0x00, "3D controller" },
85 { 0x03, 0x80, 0x00, "Other display controller" },
87 // Base Class 04h - Multimedia devices
88 { 0x04, 0x00, 0x00, "Video device - vendor specific interface" },
89 { 0x04, 0x01, 0x00, "Audio device - vendor specific interface" },
91 "Computer telephony device - vendor specific interface" },
92 { 0x04, 0x03, 0x00, "High Definition Audio (HD-A) 1.0 compatible" },
94 "High Definition Audio (HD-A) 1.0 compatible with vendor extensions" },
96 "Other multimedia device - vendor specific interface" },
97 // Base Class 05h - Memory controllers
100 { 0x05, 0x02, 0x00, "CXL Memory Device - vendor specific interface" },
103 { 0x05, 0x80, 0x00, "Other memory controller" },
105 // Base Class 06h - Bridge devices
110 { 0x06, 0x04, 0x00, "PCI-to-PCI bridge" },
111 { 0x06, 0x04, 0x01, "Subtractive Decode PCI-to-PCI bridge" },
117 "Semi-transparent PCI-to-PCI bridge - primary bus towards host" },
119 "Semi-transparent PCI-to-PCI bridge - secondary bus towards host" },
120 { 0x06, 0x0A, 0x00, "InfiniBand-to-PCI host bridge" },
122 "Advanced Switching to PCI host bridge - Custom Interface" },
124 "Advanced Switching to PCI host bridge - ASI-SIG Defined Portal Interface" },
127 // Base Class 07h - Simple communication controllers
128 { 0x07, 0x00, 0x00, "Generic XT-compatible serial controller" },
129 { 0x07, 0x00, 0x01, "16450-compatible serial controller" },
130 { 0x07, 0x00, 0x02, "16550-compatible serial controller" },
131 { 0x07, 0x00, 0x03, "16650-compatible serial controller" },
132 { 0x07, 0x00, 0x04, "16750-compatible serial controller" },
133 { 0x07, 0x00, 0x05, "16850-compatible serial controller" },
134 { 0x07, 0x00, 0x06, "16950-compatible serial controller" },
136 { 0x07, 0x01, 0x01, "Bi-directional parallel port" },
138 { 0x07, 0x01, 0x03, "IEEE1284 controller" },
140 { 0x07, 0x02, 0x00, "Multiport serial controller" },
143 "Hayes compatible modem - 16450-compatible interface" },
145 "Hayes compatible modem - 16550-compatible interface" },
147 "Hayes compatible modem - 16650-compatible interface" },
149 "Hayes compatible modem - 16750-compatible interface" },
150 { 0x07, 0x04, 0x00, "GPIB (IEEE 488.1/2) controller" },
154 // Base Class 08h - Base system peripherals
158 { 0x08, 0x00, 0x10, "I/O APIC interrupt controller" },
159 { 0x08, 0x00, 0x20, "I/O(x) APIC interrupt controller" },
160 { 0x08, 0x01, 0x00, "Generic 8237 DMA controller" },
161 { 0x08, 0x01, 0x01, "ISA DMA controller" },
162 { 0x08, 0x01, 0x02, "EISA DMA controller" },
167 { 0x08, 0x03, 0x00, "Generic RTC controller" },
168 { 0x08, 0x03, 0x01, "ISA RTC controller" },
169 { 0x08, 0x04, 0x00, "Generic PCI Hot-Plug controller" },
170 { 0x08, 0x05, 0x00, "SD Host controller" },
173 { 0x08, 0x08, 0x00, "Time Card - vendor-specific interface" },
174 { 0x08, 0x08, 0x01, "Time Card - OCP TAP interface" },
177 // Base Class 09h - Input devices
178 { 0x09, 0x00, 0x00, "Keyboard controller" },
180 { 0x09, 0x02, 0x00, "Mouse controller" },
181 { 0x09, 0x03, 0x00, "Scanner controller" },
182 { 0x09, 0x04, 0x00, "Gameport controller (generic)" },
183 { 0x09, 0x04, 0x10, "Gameport controller - legacy ports" },
184 { 0x09, 0x80, 0x00, "Other input controller" },
186 // Base Class 0Ah - Docking stations
190 // Base Class 0Bh - Processors
197 { 0x0B, 0x40, 0x00, "Co-processor" },
200 // Base Class 0Ch - Serial bus controllers
205 { 0x0C, 0x03, 0x00, "USB - Universal Host Controller Specification" },
206 { 0x0C, 0x03, 0x10, "USB - Open Host Controller Specification" },
207 { 0x0C, 0x03, 0x20, "USB2 host controller - Intel EHCI" },
208 { 0x0C, 0x03, 0x30, "USB3 host controller - Intel xHCI" },
210 { 0x0C, 0x03, 0x80, "USB - no specific Programming Interface" },
211 { 0x0C, 0x03, 0xFE, "USB device (not host controller)" },
215 { 0x0C, 0x07, 0x01, "IPMI Keyboard Controller Style Interface" },
219 { 0x0C, 0x0A, 0x00, "MIPI I3C Host Controller Interface" },
220 { 0x0C, 0x0B, 0x00, "CXL Fabric Management Host Interface controller" },
224 // Base Class 0Dh - Wireless controllers
225 { 0x0D, 0x00, 0x00, "iRDA compatible controller" },
226 { 0x0D, 0x01, 0x00, "Consumer IR controller" },
227 { 0x0D, 0x01, 0x10, "UWB Radio controller" },
228 { 0x0D, 0x10, 0x00, "RF controller" },
231 { 0x0D, 0x20, 0x00, "Ethernet (802.11a - 5 GHz)" },
232 { 0x0D, 0x21, 0x00, "Ethernet (802.11b - 2.4 GHz)" },
233 { 0x0D, 0x40, 0x00, "Cellular controller/modem" },
235 "Cellular controller/modem plus Ethernet (802.11)" },
236 { 0x0D, 0x80, 0x00, "Other type of wireless controller" },
238 // Base Class 0Eh - Intelligent I/O controllers
243 // Base Class 0Fh - Satellite communication controllers
248 { 0x0F, 0x80, 0x00, "Other satellite communication controller" },
250 // Base Class 10h - Encryption/Decryption controllers
252 "Network and computing encryption and decryption controller" },
254 "Entertainment encryption and decryption controller" },
256 { 0x10, 0x80, 0x00, "Other encryption and decryption controller" },
258 // Base Class 11h - Data acquisition and signal processing controllers
267 // Base Class 12h - Processing accelerators
269 "Processing Accelerator - vendor-specific interface" },
271 "SNIA Smart Data Accelerator Interface (SDXI) controller" },
273 // Base Class 13h - Non-Essential Instrumentation
275 "Non-Essential Instrumentation Function - Vendor specific interface" },
277 // Base Class FFh - Device does not fit in any defined classes
320 .value.ui64 = pcie_error->ValidFields }; in cper_section_pcie_to_ir()
325 pcie_error->PortType, 9, PCIE_ERROR_PORT_TYPES_KEYS, in cper_section_pcie_to_ir()
335 pcie_error->Version & 0xFF))); in cper_section_pcie_to_ir()
338 pcie_error->Version >> 8))); in cper_section_pcie_to_ir()
347 json_object_new_uint64(pcie_error->CommandStatus & in cper_section_pcie_to_ir()
351 json_object_new_uint64(pcie_error->CommandStatus >> in cper_section_pcie_to_ir()
361 UINT64 class_id = (pcie_error->DevBridge.ClassCode[2] << 16) + in cper_section_pcie_to_ir()
362 (pcie_error->DevBridge.ClassCode[1] << 8) + in cper_section_pcie_to_ir()
363 pcie_error->DevBridge.ClassCode[0]; in cper_section_pcie_to_ir()
365 get_class_code_name(pcie_error->DevBridge.ClassCode[2], in cper_section_pcie_to_ir()
366 pcie_error->DevBridge.ClassCode[1], in cper_section_pcie_to_ir()
367 pcie_error->DevBridge.ClassCode[0]); in cper_section_pcie_to_ir()
374 pcie_error->DevBridge.DeviceId); in cper_section_pcie_to_ir()
376 pcie_error->DevBridge.VendorId); in cper_section_pcie_to_ir()
379 pcie_error->DevBridge.Function); in cper_section_pcie_to_ir()
381 pcie_error->DevBridge.Device); in cper_section_pcie_to_ir()
383 pcie_error->DevBridge.Segment); in cper_section_pcie_to_ir()
385 pcie_error->DevBridge.PrimaryOrDeviceBus); in cper_section_pcie_to_ir()
387 pcie_error->DevBridge.SecondaryBus); in cper_section_pcie_to_ir()
389 pcie_error->DevBridge.Slot.Number); in cper_section_pcie_to_ir()
390 add_int(device_id, "deviceID", pcie_error->DevBridge.DeviceId); in cper_section_pcie_to_ir()
392 add_int(device_id, "vendorID", pcie_error->DevBridge.VendorId); in cper_section_pcie_to_ir()
397 pcie_error->DevBridge.Function); in cper_section_pcie_to_ir()
400 pcie_error->DevBridge.Device); in cper_section_pcie_to_ir()
403 pcie_error->DevBridge.Segment); in cper_section_pcie_to_ir()
406 pcie_error->DevBridge.PrimaryOrDeviceBus); in cper_section_pcie_to_ir()
409 pcie_error->DevBridge.SecondaryBus); in cper_section_pcie_to_ir()
412 pcie_error->DevBridge.Slot.Number); in cper_section_pcie_to_ir()
421 json_object_new_uint64(pcie_error->SerialNo)); in cper_section_pcie_to_ir()
429 json_object_new_uint64(pcie_error->BridgeControlStatus & in cper_section_pcie_to_ir()
434 pcie_error->BridgeControlStatus >> 16)); in cper_section_pcie_to_ir()
441 //(36-byte, padded to 60 bytes) or PCIe 2.0 Capability Structure (60-byte). in cper_section_pcie_to_ir()
464 encoded = base64_encode((UINT8 *)pcie_error->Capability.PcieCap, 60, in pcie_capability_to_ir()
477 cap_decode = (capability_registers *)&pcie_error->Capability.PcieCap; in pcie_capability_to_ir()
485 &cap_decode->pcie_capability_header; in pcie_capability_to_ir()
486 add_dict(fields_ir, "capability_id", pcie_cap_header->capability_id, in pcie_capability_to_ir()
489 pcie_cap_header->next_capability_pointer); in pcie_capability_to_ir()
498 pcie_capabilities_t *pcie_cap = &cap_decode->pcie_capabilities; in pcie_capability_to_ir()
499 add_int(fields_ir, "capability_version", pcie_cap->capability_version); in pcie_capability_to_ir()
500 add_dict(fields_ir, "device_port_type", pcie_cap->device_port_type, in pcie_capability_to_ir()
502 add_bool(fields_ir, "slot_implemented", pcie_cap->slot_implemented); in pcie_capability_to_ir()
504 pcie_cap->interrupt_message_number); in pcie_capability_to_ir()
505 //add_int(fields_ir, "undefined", pcie_cap->undefined); in pcie_capability_to_ir()
507 pcie_cap->flit_mode_supported); in pcie_capability_to_ir()
517 cap_decode->device_capabilities.max_payload_size_supported); in pcie_capability_to_ir()
520 cap_decode->device_capabilities.phantom_functions_supported); in pcie_capability_to_ir()
523 cap_decode->device_capabilities.extended_tag_field_supported); in pcie_capability_to_ir()
526 cap_decode->device_capabilities.endpoint_l0s_acceptable_latency, in pcie_capability_to_ir()
529 cap_decode->device_capabilities.endpoint_l1_acceptable_latency, in pcie_capability_to_ir()
532 // cap_decode->device_capabilities.undefined); in pcie_capability_to_ir()
534 cap_decode->device_capabilities.role_based_error_reporting); in pcie_capability_to_ir()
536 cap_decode->device_capabilities.err_cor_subclass_capable); in pcie_capability_to_ir()
538 cap_decode->device_capabilities.rx_mps_fixed); in pcie_capability_to_ir()
540 cap_decode->device_capabilities.captured_slot_power_limit_value); in pcie_capability_to_ir()
542 cap_decode->device_capabilities.captured_slot_power_limit_scale); in pcie_capability_to_ir()
546 cap_decode->device_capabilities.function_level_reset_capability); in pcie_capability_to_ir()
548 cap_decode->device_capabilities.mixed_mps_supported); in pcie_capability_to_ir()
550 cap_decode->device_capabilities.tee_io_supported); in pcie_capability_to_ir()
551 //add_int(fields_ir, "rsvdp", cap_decode->device_capabilities.rsvdp); in pcie_capability_to_ir()
562 cap_decode->device_control.correctable_error_reporting_enable); in pcie_capability_to_ir()
565 cap_decode->device_control.non_fatal_error_reporting_enable); in pcie_capability_to_ir()
567 cap_decode->device_control.fatal_error_reporting_enable); in pcie_capability_to_ir()
571 cap_decode->device_control.unsupported_request_reporting_enable); in pcie_capability_to_ir()
573 cap_decode->device_control.enable_relaxed_ordering); in pcie_capability_to_ir()
575 cap_decode->device_control.max_payload_size); in pcie_capability_to_ir()
577 cap_decode->device_control.extended_tag_field_enable); in pcie_capability_to_ir()
579 cap_decode->device_control.phantom_functions_enable); in pcie_capability_to_ir()
581 cap_decode->device_control.aux_power_pm_enable); in pcie_capability_to_ir()
583 cap_decode->device_control.enable_no_snoop); in pcie_capability_to_ir()
585 cap_decode->device_control.max_read_request_size); in pcie_capability_to_ir()
587 cap_decode->device_control.function_level_reset); in pcie_capability_to_ir()
596 cap_decode->device_status.correctable_error_detected); in pcie_capability_to_ir()
598 cap_decode->device_status.non_fatal_error_detected); in pcie_capability_to_ir()
600 cap_decode->device_status.fatal_error_detected); in pcie_capability_to_ir()
602 cap_decode->device_status.unsupported_request_detected); in pcie_capability_to_ir()
604 cap_decode->device_status.aux_power_detected); in pcie_capability_to_ir()
606 cap_decode->device_status.transactions_pending); in pcie_capability_to_ir()
608 cap_decode->device_status.emergency_power_reduction); in pcie_capability_to_ir()
609 //add_int(fields_ir, "rsvdz", cap_decode->device_status.rsvdz); in pcie_capability_to_ir()
618 cap_decode->link_capabilities.max_link_speed); in pcie_capability_to_ir()
620 cap_decode->link_capabilities.maximum_link_width); in pcie_capability_to_ir()
622 cap_decode->link_capabilities.aspm_support); in pcie_capability_to_ir()
624 cap_decode->link_capabilities.l0s_exit_latency); in pcie_capability_to_ir()
626 cap_decode->link_capabilities.l1_exit_latency); in pcie_capability_to_ir()
628 cap_decode->link_capabilities.clock_power_management); in pcie_capability_to_ir()
630 cap_decode->link_capabilities in pcie_capability_to_ir()
633 cap_decode->link_capabilities in pcie_capability_to_ir()
636 cap_decode->link_capabilities in pcie_capability_to_ir()
639 cap_decode->link_capabilities.aspm_optionality_compliance); in pcie_capability_to_ir()
640 //add_int(fields_ir, "rsvdp", cap_decode->link_capabilities.rsvdp); in pcie_capability_to_ir()
642 cap_decode->link_capabilities.port_number); in pcie_capability_to_ir()
652 cap_decode->link_control.aspm_control); in pcie_capability_to_ir()
654 cap_decode->link_control in pcie_capability_to_ir()
657 // cap_decode->link_control.read_completion_boundary); in pcie_capability_to_ir()
659 cap_decode->link_control.link_disable); in pcie_capability_to_ir()
661 cap_decode->link_control.retrain_link); in pcie_capability_to_ir()
663 // cap_decode->link_control.common_clock_configuration); in pcie_capability_to_ir()
665 cap_decode->link_control.extended_synch); in pcie_capability_to_ir()
667 // cap_decode->link_control.enable_clock_power_management); in pcie_capability_to_ir()
669 // cap_decode->link_control.hardware_autonomous_width_disable); in pcie_capability_to_ir()
671 // cap_decode->link_control in pcie_capability_to_ir()
674 // cap_decode->link_control in pcie_capability_to_ir()
677 cap_decode->link_control.sris_clocking); in pcie_capability_to_ir()
679 cap_decode->link_control.flit_mode_disable); in pcie_capability_to_ir()
681 // cap_decode->link_control.drs_signaling_control); in pcie_capability_to_ir()
690 cap_decode->link_status.current_link_speed); in pcie_capability_to_ir()
692 cap_decode->link_status.negotiated_link_width); in pcie_capability_to_ir()
693 //add_int(fields_ir, "undefined", cap_decode->link_status.undefined); in pcie_capability_to_ir()
695 cap_decode->link_status.link_training); in pcie_capability_to_ir()
697 // cap_decode->link_status.slot_clock_configuration); in pcie_capability_to_ir()
699 // cap_decode->link_status.data_link_layer_link_active); in pcie_capability_to_ir()
701 // cap_decode->link_status.link_bandwidth_management_status); in pcie_capability_to_ir()
703 // cap_decode->link_status.link_autonomous_bandwidth_status); in pcie_capability_to_ir()
712 // cap_decode->slot_capabilities.attention_button_present); in pcie_capability_to_ir()
714 // cap_decode->slot_capabilities.power_controller_present); in pcie_capability_to_ir()
716 // cap_decode->slot_capabilities.mrl_sensor_present); in pcie_capability_to_ir()
718 // cap_decode->slot_capabilities.attention_indicator_present); in pcie_capability_to_ir()
720 // cap_decode->slot_capabilities.power_indicator_present); in pcie_capability_to_ir()
722 // cap_decode->slot_capabilities.hot_plug_surprise); in pcie_capability_to_ir()
724 // cap_decode->slot_capabilities.hot_plug_capable); in pcie_capability_to_ir()
726 cap_decode->slot_capabilities.slot_power_limit_value, NULL, 0); in pcie_capability_to_ir()
728 cap_decode->slot_capabilities.slot_power_limit_scale); in pcie_capability_to_ir()
730 // cap_decode->slot_capabilities in pcie_capability_to_ir()
733 // cap_decode->slot_capabilities.no_command_completed_support); in pcie_capability_to_ir()
735 cap_decode->slot_capabilities.physical_slot_number); in pcie_capability_to_ir()
745 // cap_decode->slot_control.attention_button_pressed_enable); in pcie_capability_to_ir()
747 // cap_decode->slot_control.power_fault_detected_enable); in pcie_capability_to_ir()
749 // cap_decode->slot_control.mrl_sensor_changed_enable); in pcie_capability_to_ir()
751 // cap_decode->slot_control.presence_detect_changed_enable); in pcie_capability_to_ir()
753 // cap_decode->slot_control.command_completed_interrupt_enable); in pcie_capability_to_ir()
755 // cap_decode->slot_control.hot_plug_interrupt_enable); in pcie_capability_to_ir()
757 cap_decode->slot_control.attention_indicator_control); in pcie_capability_to_ir()
759 cap_decode->slot_control.power_indicator_control); in pcie_capability_to_ir()
761 // cap_decode->slot_control.power_controller_control); in pcie_capability_to_ir()
763 // cap_decode->slot_control.electromechanical_interlock_control); in pcie_capability_to_ir()
765 // cap_decode->slot_control.data_link_layer_state_changed_enable); in pcie_capability_to_ir()
767 // cap_decode->slot_control.auto_slot_power_limit_disable); in pcie_capability_to_ir()
769 // cap_decode->slot_control.in_band_pd_disable); in pcie_capability_to_ir()
770 add_int(fields_ir, "rsvdp", cap_decode->slot_control.rsvdp); in pcie_capability_to_ir()
779 // cap_decode->slot_status.attention_button_pressed); in pcie_capability_to_ir()
781 // cap_decode->slot_status.power_fault_detected); in pcie_capability_to_ir()
783 cap_decode->slot_status.mrl_sensor_changed); in pcie_capability_to_ir()
785 // cap_decode->slot_status.presence_detect_changed); in pcie_capability_to_ir()
787 cap_decode->slot_status.command_completed); in pcie_capability_to_ir()
789 cap_decode->slot_status.mrl_sensor_state); in pcie_capability_to_ir()
791 // cap_decode->slot_status.presence_detect_state); in pcie_capability_to_ir()
793 // cap_decode->slot_status.electromechanical_interlock_status); in pcie_capability_to_ir()
795 // cap_decode->slot_status.data_link_layer_state_changed); in pcie_capability_to_ir()
796 //add_int(fields_ir, "rsvdz", cap_decode->slot_status.rsvdz); in pcie_capability_to_ir()
805 // cap_decode->root_control in pcie_capability_to_ir()
809 // cap_decode->root_control.system_error_on_non_fatal_error_enable); in pcie_capability_to_ir()
811 // cap_decode->root_control.system_error_on_fatal_error_enable); in pcie_capability_to_ir()
813 // cap_decode->root_control.pme_interrupt_enable); in pcie_capability_to_ir()
815 // cap_decode->root_control in pcie_capability_to_ir()
818 // cap_decode->root_control.no_nfm_subtree_below_this_root_port); in pcie_capability_to_ir()
819 //add_int(fields_ir, "rsvdp", cap_decode->root_control.rsvdp); in pcie_capability_to_ir()
828 // cap_decode->root_capabilities in pcie_capability_to_ir()
830 //add_int(fields_ir, "rsvdp", cap_decode->root_capabilities.rsvdp); in pcie_capability_to_ir()
840 cap_decode->root_status.pme_requester_id); in pcie_capability_to_ir()
841 add_int(fields_ir, "pme_status", cap_decode->root_status.pme_status); in pcie_capability_to_ir()
842 add_int(fields_ir, "pme_pending", cap_decode->root_status.pme_pending); in pcie_capability_to_ir()
843 //add_int(fields_ir, "rsvdp", cap_decode->root_status.rsvdp); in pcie_capability_to_ir()
846 if (cap_decode->pcie_capabilities.capability_version < 2) { in pcie_capability_to_ir()
856 cap_decode->device_capabilities2 in pcie_capability_to_ir()
860 cap_decode->device_capabilities2 in pcie_capability_to_ir()
864 cap_decode->device_capabilities2.ari_forwarding_supported); in pcie_capability_to_ir()
867 cap_decode->device_capabilities2.atomic_op_routing_supported); in pcie_capability_to_ir()
870 cap_decode->device_capabilities2 in pcie_capability_to_ir()
874 cap_decode->device_capabilities2 in pcie_capability_to_ir()
878 cap_decode->device_capabilities2 in pcie_capability_to_ir()
882 cap_decode->device_capabilities2.no_ro_enabled_pr_pr_passing); in pcie_capability_to_ir()
884 cap_decode->device_capabilities2.ltr_mechanism_supported); in pcie_capability_to_ir()
886 cap_decode->device_capabilities2.tph_completer_supported); in pcie_capability_to_ir()
888 // cap_decode->device_capabilities2.undefined); in pcie_capability_to_ir()
890 // cap_decode->device_capabilities2 in pcie_capability_to_ir()
893 // cap_decode->device_capabilities2 in pcie_capability_to_ir()
896 cap_decode->device_capabilities2.obff_supported); in pcie_capability_to_ir()
898 // cap_decode->device_capabilities2.extended_fmt_field_supported); in pcie_capability_to_ir()
900 // cap_decode->device_capabilities2.end_end_tlp_prefix_supported); in pcie_capability_to_ir()
902 cap_decode->device_capabilities2.max_end_end_tlp_prefixes, in pcie_capability_to_ir()
906 cap_decode->device_capabilities2 in pcie_capability_to_ir()
909 // cap_decode->device_capabilities2 in pcie_capability_to_ir()
911 //add_int(fields_ir, "rsvdp", cap_decode->device_capabilities2.rsvdp); in pcie_capability_to_ir()
913 // cap_decode->device_capabilities2.dmwr_completer_supported); in pcie_capability_to_ir()
915 cap_decode->device_capabilities2.dmwr_lengths_supported); in pcie_capability_to_ir()
917 // cap_decode->device_capabilities2.frs_supported); in pcie_capability_to_ir()
927 cap_decode->device_control2.completion_timeout_value); in pcie_capability_to_ir()
929 // cap_decode->device_control2.completion_timeout_disable); in pcie_capability_to_ir()
931 cap_decode->device_control2.ari_forwarding_enable); in pcie_capability_to_ir()
933 cap_decode->device_control2.atomicop_requester_enable); in pcie_capability_to_ir()
935 cap_decode->device_control2.atomicop_egress_blocking); in pcie_capability_to_ir()
937 cap_decode->device_control2.ido_request_enable); in pcie_capability_to_ir()
939 cap_decode->device_control2.ido_completion_enable); in pcie_capability_to_ir()
941 cap_decode->device_control2.ltr_mechanism_enable); in pcie_capability_to_ir()
943 cap_decode->device_control2.emergency_power_reduction_request); in pcie_capability_to_ir()
945 cap_decode->device_control2.bit_tag_requester_10_enable); in pcie_capability_to_ir()
947 cap_decode->device_control2.obff_enable); in pcie_capability_to_ir()
949 // cap_decode->device_control2.end_end_tlp_prefix_blocking); in pcie_capability_to_ir()
958 //add_int(fields_ir, "rsvdz", cap_decode->device_status2.rsvdz); in pcie_capability_to_ir()
966 //add_int(fields_ir, "rsvdp", cap_decode->link_capabilities2.rsvdp); in pcie_capability_to_ir()
968 cap_decode->link_capabilities2.supported_link_speeds_register); in pcie_capability_to_ir()
970 cap_decode->link_capabilities2.crosslink_supported); in pcie_capability_to_ir()
972 cap_decode->link_capabilities2 in pcie_capability_to_ir()
975 cap_decode->link_capabilities2.lower_skp_os_reception_supported); in pcie_capability_to_ir()
978 cap_decode->link_capabilities2 in pcie_capability_to_ir()
982 cap_decode->link_capabilities2 in pcie_capability_to_ir()
984 //add_int(fields_ir, "reserved", cap_decode->link_capabilities2.reserved); in pcie_capability_to_ir()
986 cap_decode->link_capabilities2.drs_supported); in pcie_capability_to_ir()
996 cap_decode->link_control2.target_link_speed, NULL, 0); in pcie_capability_to_ir()
998 cap_decode->link_control2.enter_compliance); in pcie_capability_to_ir()
1000 cap_decode->link_control2.hardware_autonomous_speed_disable, in pcie_capability_to_ir()
1003 cap_decode->link_control2.selectable_de_emphasis); in pcie_capability_to_ir()
1005 cap_decode->link_control2.transmit_margin); in pcie_capability_to_ir()
1007 cap_decode->link_control2.enter_modified_compliance); in pcie_capability_to_ir()
1009 cap_decode->link_control2.compliance_sos); in pcie_capability_to_ir()
1011 cap_decode->link_control2.compliance_preset_de_emphasis); in pcie_capability_to_ir()
1020 cap_decode->link_status2.current_de_emphasis_level); in pcie_capability_to_ir()
1022 cap_decode->link_status2.equalization_8gts_complete); in pcie_capability_to_ir()
1024 cap_decode->link_status2.equalization_8gts_phase1_successful); in pcie_capability_to_ir()
1026 cap_decode->link_status2.equalization_8gts_phase2_successful); in pcie_capability_to_ir()
1028 cap_decode->link_status2.equalization_8gts_phase3_successful); in pcie_capability_to_ir()
1030 cap_decode->link_status2.link_equalization_request_8gts); in pcie_capability_to_ir()
1032 cap_decode->link_status2.retimer_presence_detected); in pcie_capability_to_ir()
1034 cap_decode->link_status2.two_retimers_presence_detected); in pcie_capability_to_ir()
1036 cap_decode->link_status2.crosslink_resolution); in pcie_capability_to_ir()
1038 cap_decode->link_status2.flit_mode_status); in pcie_capability_to_ir()
1039 //add_int(fields_ir, "rsvdz", cap_decode->link_status2.rsvdz); in pcie_capability_to_ir()
1041 cap_decode->link_status2.downstream_component_presence); in pcie_capability_to_ir()
1043 cap_decode->link_status2.drs_message_received); in pcie_capability_to_ir()
1051 //add_int(fields_ir, "rsvdp", cap_decode->slot_capabilities2.rsvdp); in pcie_capability_to_ir()
1060 //add_int(fields_ir, "rsvdp", cap_decode->slot_control2.rsvdp); in pcie_capability_to_ir()
1068 //add_int(fields_ir, "rsvdp", cap_decode->slot_status2.rsvdp); in pcie_capability_to_ir()
1081 encoded = base64_encode((UINT8 *)pcie_error->AerInfo.PcieAer, 96, in pcie_aer_to_ir()
1095 aer_decode = (aer_info_registers *)&pcie_error->AerInfo.PcieAer; in pcie_aer_to_ir()
1103 aer_decode->capability_header.capability_id); in pcie_aer_to_ir()
1105 aer_decode->capability_header.capability_version); in pcie_aer_to_ir()
1107 aer_decode->capability_header.next_capability_offset); in pcie_aer_to_ir()
1117 // aer_decode->uncorrectable_error_status.undefined); in pcie_aer_to_ir()
1119 // aer_decode->uncorrectable_error_status.rsvdz1); in pcie_aer_to_ir()
1121 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1124 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1127 // aer_decode->uncorrectable_error_status.rsvdz2); in pcie_aer_to_ir()
1129 aer_decode->uncorrectable_error_status.poisoned_tlp_received); in pcie_aer_to_ir()
1131 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1134 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1137 aer_decode->uncorrectable_error_status.completer_abort_status); in pcie_aer_to_ir()
1139 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1143 aer_decode->uncorrectable_error_status.receiver_overflow_status); in pcie_aer_to_ir()
1145 aer_decode->uncorrectable_error_status.malformed_tlp_status); in pcie_aer_to_ir()
1147 aer_decode->uncorrectable_error_status.ecrc_error_status); in pcie_aer_to_ir()
1149 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1152 aer_decode->uncorrectable_error_status.acs_violation_status); in pcie_aer_to_ir()
1154 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1157 aer_decode->uncorrectable_error_status.mc_blocked_tlp_status); in pcie_aer_to_ir()
1159 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1162 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1165 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1168 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1172 aer_decode->uncorrectable_error_status.ide_check_failed_status); in pcie_aer_to_ir()
1175 aer_decode->uncorrectable_error_status.misrouted_ide_tlp_status); in pcie_aer_to_ir()
1178 aer_decode->uncorrectable_error_status.pcrc_check_failed_status); in pcie_aer_to_ir()
1180 aer_decode->uncorrectable_error_status in pcie_aer_to_ir()
1191 // aer_decode->uncorrectable_error_mask.undefined); in pcie_aer_to_ir()
1193 // aer_decode->uncorrectable_error_mask.rsvdz1); in pcie_aer_to_ir()
1195 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1198 aer_decode->uncorrectable_error_mask.surprise_down_error_mask); in pcie_aer_to_ir()
1200 // aer_decode->uncorrectable_error_mask.rsvdz2); in pcie_aer_to_ir()
1202 aer_decode->uncorrectable_error_mask.poisoned_tlp_received_mask); in pcie_aer_to_ir()
1204 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1207 aer_decode->uncorrectable_error_mask.completion_timeout_mask); in pcie_aer_to_ir()
1209 aer_decode->uncorrectable_error_mask.completer_abort_mask); in pcie_aer_to_ir()
1211 aer_decode->uncorrectable_error_mask.unexpected_completion_mask); in pcie_aer_to_ir()
1213 aer_decode->uncorrectable_error_mask.receiver_overflow_mask); in pcie_aer_to_ir()
1215 aer_decode->uncorrectable_error_mask.malformed_tlp_mask); in pcie_aer_to_ir()
1217 aer_decode->uncorrectable_error_mask.ecrc_error_mask); in pcie_aer_to_ir()
1219 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1222 aer_decode->uncorrectable_error_mask.acs_violation_mask); in pcie_aer_to_ir()
1224 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1227 aer_decode->uncorrectable_error_mask.mc_blocked_tlp_mask); in pcie_aer_to_ir()
1229 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1232 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1235 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1238 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1241 aer_decode->uncorrectable_error_mask.ide_check_failed_mask); in pcie_aer_to_ir()
1243 aer_decode->uncorrectable_error_mask.misrouted_ide_tlp_mask); in pcie_aer_to_ir()
1245 aer_decode->uncorrectable_error_mask.pcrc_check_failed_mask); in pcie_aer_to_ir()
1247 aer_decode->uncorrectable_error_mask in pcie_aer_to_ir()
1258 // aer_decode->uncorrectable_error_severity.undefined); in pcie_aer_to_ir()
1260 // aer_decode->uncorrectable_error_severity.rsvdz1); in pcie_aer_to_ir()
1263 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1266 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1269 // aer_decode->uncorrectable_error_severity.rsvdz2); in pcie_aer_to_ir()
1272 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1276 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1279 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1282 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1286 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1289 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1293 aer_decode->uncorrectable_error_severity.malformed_tlp_severity); in pcie_aer_to_ir()
1296 aer_decode->uncorrectable_error_severity.ecrc_error_severity); in pcie_aer_to_ir()
1299 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1303 aer_decode->uncorrectable_error_severity.acs_violation_severity); in pcie_aer_to_ir()
1306 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1309 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1313 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1317 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1321 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1325 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1328 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1331 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1334 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1338 aer_decode->uncorrectable_error_severity in pcie_aer_to_ir()
1349 aer_decode->correctable_error_status.receiver_error_status); in pcie_aer_to_ir()
1351 // aer_decode->correctable_error_status.rsvdz1); in pcie_aer_to_ir()
1353 aer_decode->correctable_error_status.bad_tlp_status); in pcie_aer_to_ir()
1355 aer_decode->correctable_error_status.bad_dllp_status); in pcie_aer_to_ir()
1358 aer_decode->correctable_error_status.replay_num_rollover_status); in pcie_aer_to_ir()
1360 // aer_decode->correctable_error_status.rsvdz2); in pcie_aer_to_ir()
1362 aer_decode->correctable_error_status in pcie_aer_to_ir()
1365 aer_decode->correctable_error_status in pcie_aer_to_ir()
1368 aer_decode->correctable_error_status in pcie_aer_to_ir()
1372 aer_decode->correctable_error_status.header_log_overflow_status); in pcie_aer_to_ir()
1374 // aer_decode->correctable_error_status.rsvdz3); in pcie_aer_to_ir()
1384 aer_decode->correctable_error_mask.receiver_error_mask); in pcie_aer_to_ir()
1385 //add_int(fields_ir, "rsvdz1", aer_decode->correctable_error_mask.rsvdz1); in pcie_aer_to_ir()
1387 aer_decode->correctable_error_mask.bad_tlp_mask); in pcie_aer_to_ir()
1389 aer_decode->correctable_error_mask.bad_dllp_mask); in pcie_aer_to_ir()
1391 aer_decode->correctable_error_mask.replay_num_rollover_mask); in pcie_aer_to_ir()
1392 //add_int(fields_ir, "rsvdz2", aer_decode->correctable_error_mask.rsvdz2); in pcie_aer_to_ir()
1394 aer_decode->correctable_error_mask.replay_timer_timeout_mask); in pcie_aer_to_ir()
1396 aer_decode->correctable_error_mask in pcie_aer_to_ir()
1399 aer_decode->correctable_error_mask in pcie_aer_to_ir()
1402 aer_decode->correctable_error_mask.header_log_overflow_mask); in pcie_aer_to_ir()
1403 //add_int(fields_ir, "rsvdz3", aer_decode->correctable_error_mask.rsvdz3); in pcie_aer_to_ir()
1413 aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1416 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1419 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1422 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1425 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1428 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1431 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1434 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1437 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1440 aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1443 // aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1446 aer_decode->advanced_error_capabilities_and_control in pcie_aer_to_ir()
1449 // aer_decode->advanced_error_capabilities_and_control.rsvdp); in pcie_aer_to_ir()
1460 // aer_decode->root_error_command in pcie_aer_to_ir()
1464 // aer_decode->root_error_command.non_fatal_error_reporting_enable); in pcie_aer_to_ir()
1466 // aer_decode->root_error_command.fatal_error_reporting_enable); in pcie_aer_to_ir()
1467 //add_int(fields_ir, "rsvdp", aer_decode->root_error_command.rsvdp); in pcie_aer_to_ir()
1477 // aer_decode->root_error_status.err_cor_received); in pcie_aer_to_ir()
1479 // aer_decode->root_error_status.multiple_err_cor_received); in pcie_aer_to_ir()
1481 // aer_decode->root_error_status.err_fatal_nonfatal_received); in pcie_aer_to_ir()
1483 // aer_decode->root_error_status in pcie_aer_to_ir()
1486 // aer_decode->root_error_status.first_uncorrectable_fatal); in pcie_aer_to_ir()
1489 // aer_decode->root_error_status.non_fatal_error_messages_received); in pcie_aer_to_ir()
1491 // aer_decode->root_error_status.fatal_error_messages_received); in pcie_aer_to_ir()
1493 aer_decode->root_error_status.err_cor_subclass); in pcie_aer_to_ir()
1494 //add_int(fields_ir, "rsvdz", aer_decode->root_error_status.rsvdz); in pcie_aer_to_ir()
1496 aer_decode->root_error_status in pcie_aer_to_ir()
1507 aer_decode->error_source_id.err_cor_source_identification); in pcie_aer_to_ir()
1509 aer_decode->error_source_id in pcie_aer_to_ir()
1516 //Converts a single CPER-JSON PCIe section into CPER binary, outputting to the given stream.
1533 section_cper->Version = minor + (major << 8); in ir_section_pcie_to_cper()
1546 section_cper->CommandStatus = command + (status << 16); in ir_section_pcie_to_cper()
1555 section_cper->DevBridge.VendorId = in ir_section_pcie_to_cper()
1558 section_cper->DevBridge.DeviceId = in ir_section_pcie_to_cper()
1561 section_cper->DevBridge.ClassCode[2] = class_id >> 16; in ir_section_pcie_to_cper()
1562 section_cper->DevBridge.ClassCode[1] = (class_id >> 8) & 0xFF; in ir_section_pcie_to_cper()
1563 section_cper->DevBridge.ClassCode[0] = class_id & 0xFF; in ir_section_pcie_to_cper()
1564 section_cper->DevBridge.Function = in ir_section_pcie_to_cper()
1567 section_cper->DevBridge.Device = (UINT8)json_object_get_uint64( in ir_section_pcie_to_cper()
1569 section_cper->DevBridge.Segment = in ir_section_pcie_to_cper()
1572 section_cper->DevBridge.PrimaryOrDeviceBus = in ir_section_pcie_to_cper()
1575 section_cper->DevBridge.SecondaryBus = in ir_section_pcie_to_cper()
1578 section_cper->DevBridge.Slot.Number = in ir_section_pcie_to_cper()
1593 section_cper->BridgeControlStatus = in ir_section_pcie_to_cper()
1613 memcpy(section_cper->Capability.PcieCap, decoded, in ir_section_pcie_to_cper()
1636 memcpy(section_cper->AerInfo.PcieAer, decoded, in ir_section_pcie_to_cper()
1645 section_cper->PortType = (UINT32)readable_pair_to_integer(obj); in ir_section_pcie_to_cper()
1649 section_cper->SerialNo = json_object_get_uint64(obj); in ir_section_pcie_to_cper()
1653 section_cper->ValidFields = ui64Type.value.ui64; in ir_section_pcie_to_cper()