entity-manager/docs/address_size_detection_modes.md

6 ## MODE-1
8 The existing upstream function isDevice16Bit() bases on sending 1-byte write
9 operation (with a STOP condition) and 8 subsequent 1-byte read operations with
12 ### This MODE-1 expects the following logic
14 - If the device requires 1 address byte, it EXPECTS that the data will be read
16 - If the device requires 2 address bytes, it EXPECTS that the data will be read
20 ### Issue and potential issue with this MODE-1
22 - If any "2 address bytes" EEPROM from any vendor has the same data in all
23   memory locations (0-7) the existing upstream function read, this device will
26 - ONSEMI EEPROM (a 2 address bytes device) return the same data from the same
27   single byte address read --> therefore, existing function wrongly identifies
30 ## MODE-2
32 The proposal MODE-2 changes to isDevice16Bit() sends 8 instructions of 2-bytes
34 1-byte read operation. The proposed solution fully complies with IIC standard
39 `|-------|---------------|------|------|----------------------|-------| --------------|-----------|…
49 - If the device requires a single data byte, then it will always load address
54 - If two address bytes are required, then the device will interpret both bytes
62 the 1-byte address devices will start internal write cycle, altering the EEPROM
65 This proposal MODE-2 suffers the same 1st issue as MODE-1 ie. what if the EEPROM
66 has the same data at all those addresses. However, this proposal MODE-2
67 addresses the 2nd issue of MODE-1 which expects that the data will be read from
69 is the ambiguity (not standard defined) in the IIC specification.
71 In [IIC specification:](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)
73 - Section 3.1.10, Note 2 ->
74 …`All decisions on auto-increment or decrement of previously accessed memory locations, etc., are t…
80   Based on this, the others EEPROM (not ONSEMI EEPROM) auto-increment - observed
81   with one address byte sent instead of two - is a manufacturer-specific
82   behavior, and not standard defined.
84 - Section 3.1.10, Note 1 ->
87   This proposal MODE-2 implements this note. The memory location referred herein