| #
fb651b10 |
| 14-May-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
|
| #
04bccc3a |
| 25-Mar-2013 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
T4240/net: use QSGMII card PHY address by default
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
S
T4240/net: use QSGMII card PHY address by default
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
95927808 |
| 25-Mar-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
s
t4240qds/eth: fixup ethernet for t4240qds
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
10d644b1 |
| 25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc: Add T4160QDS
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDe
powerpc: Add T4160QDS
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
97c7fe61 |
| 25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/t4240qds: Add voltage ID support
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.
powerpc/t4240qds: Add voltage ID support
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
4e5c9261 |
| 25-Mar-2013 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix XAUI card PHY address
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <a
powerpc/t4240qds: fix XAUI card PHY address
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
7ff8c7ce |
| 25-Mar-2013 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: Fix SPI flash type
T4240QDS uses a SST instead of SPANSION SPI flash.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <aflem
powerpc/t4240qds: Fix SPI flash type
T4240QDS uses a SST instead of SPANSION SPI flash.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
9cd9b34d |
| 23-Feb-2013 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
951c6baa |
| 12-Feb-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
b6832af8 |
| 30-Jan-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
|
| #
9730b7bc |
| 19-Dec-2012 |
York Sun <yorksun@freescale.com> |
powerpc/t4240qds: Update IFC timing for NOR flash
Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.
Signed-off-by: York
powerpc/t4240qds: Update IFC timing for NOR flash
Relax parameters to give address latching more time to setup.
Tighten parameters to make it overall faster.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
9427ba5c |
| 18-Dec-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/T4240qds:Fix IFC AMASK init as per FPGA register space
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.
boards/T4240qds:Fix IFC AMASK init as per FPGA register space
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's
Address Mask Registers is initialised 64K size.
So Fix the Address Mask Register initilisation as 4K
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
3e4d27b0 |
| 10-Nov-2012 |
Stefano Babic <sbabic@denx.de> |
Merge git://git.denx.de/u-boot
|
| #
a42c87f9 |
| 03-Nov-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-ti/master'
|
| #
f04821a8 |
| 27-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-imx/master'
|
| #
4c257613 |
| 26-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-atmel/master'
|
| #
c68436fa |
| 26-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-ti/master'
|
| #
71724830 |
| 22-Oct-2012 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fdt
|
| #
c7656bab |
| 22-Oct-2012 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
|
| #
ee52b188 |
| 11-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/t4qds: Add T4QDS board
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
S
powerpc/t4qds: Add T4QDS board
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
SERDES Connections
32 lanes grouped into four 8-lane banks
Two “front side” banks dedicated to Ethernet
Two “back side” banks dedicated to other protocols
DDR Controllers
Three independant 64-bit DDR3 controllers
Supports rates up to 2133 MHz data-rate
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA
Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.
Detail information can be found in doc/README.t4qds
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|