Merge branch 'master' of git://git.denx.de/u-boot-nios

* 'master' of git://git.denx.de/u-boot-nios:
nios2 - adjust gbl data off to account for bd_info
nios2: implement get_ticks

Merge branch 'master' of git://git.denx.de/u-boot-nios

* 'master' of git://git.denx.de/u-boot-nios:
nios2 - adjust gbl data off to account for bd_info
nios2: implement get_ticks and get_tbclk
nios2: add flush_dcache_range function

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pci: move pciauto_config_init() to pci.h

Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init()

pci: move pciauto_config_init() to pci.h

Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in <pci.h>
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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pci: move pcidelay code to new location just before PCI bus scan

PCI cards might need some time after reset to respond. On some
boards (mpc5200 or mpc8260 based) the PCI bus reset is dea

pci: move pcidelay code to new location just before PCI bus scan

PCI cards might need some time after reset to respond. On some
boards (mpc5200 or mpc8260 based) the PCI bus reset is deasserted
at pci_init_board() time, so we currently can not use available
"pcidelay" option for waiting before PCI bus scan since this
waiting takes place before calling pci_init_board(). By moving
the pcidelay code to the new location using of the "pcidelay"
option is possible on mpc5200 or mpc8260 based boards, too.

Since pci_hose_scan() could be called multiple times, restrict
the function to wait only during its first call and to ignore
pcidelay for any further call (as pointed out by Matthias).

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
run arm_pci_init after relocation
IXP42x PCI rewrite
update/fix PDNB3 boar

Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
run arm_pci_init after relocation
IXP42x PCI rewrite
update/fix PDNB3 board
update/fix IXDP425 / IXDPG425 boards
add dvlhost (dLAN 200 AV Wireless G) board
IXP NPE: add support for fixed-speed MII ports
update/fix AcTux4 board
update/fix AcTux3 board
update/fix AcTux2 board
update/fix AcTux1 board
use -ffunction-sections / --gc-sections on IXP42x
support CONFIG_SYS_LDSCRIPT on ARM
fix "depend" target in npe directory
Fix IXP code to work after relocation was added
trigger hardware watchdog in IXP42x serial driver
add support for IXP42x Rev. B1 and newer
add XScale sub architecture (IXP/PXA) to maintainer list

Conflicts:
arch/arm/lib/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

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IXP42x PCI rewrite

clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead. Move board-specific PCI
setup code (

IXP42x PCI rewrite

clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead. Move board-specific PCI
setup code (clock/reset) to board directory.

Signed-off-by: Michael Schwingen <michael@schwingen.org>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup

Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular P

powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup

Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.

Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>

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Merge branch 'master' of git://git.denx.de/u-boot-samsung

Merge branch 'master' of git://git.denx.de/u-boot-arm

pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOW

When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as
they are found during bootup, eg:
PCIE1: connected a

pci: Use intelligent indentation for CONFIG_PCI_SCAN_SHOW

When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as
they are found during bootup, eg:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d

This information is useful, but its difficult to determine the PCI bus
topology. To things clearer, we can use indention to make it more
obvious how the PCI bus is organized. For the example above, the
updated output with this change is:

PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d

In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch
(01:00 and 02:0x), which is connected to another PEX8518 PCIe switch
(06:00 and 07:0x), which then connects to a MPC8572 processor (08:00).
Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet
card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

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pci: Fix ordering of devices when CONFIG_PCI_SCAN_SHOW

Move the printing of PCI device information to before the PCI device is
configured. This prevents the case where recursive scannin

pci: Fix ordering of devices when CONFIG_PCI_SCAN_SHOW

Move the printing of PCI device information to before the PCI device is
configured. This prevents the case where recursive scanning results in
the deepest devices being printed first.

This change also makes PCI lockups during enumeration easier to
diagnose since the device that is being configured is printed out prior
to configuration. Previously, it was not possible to determine which
device caused the PCI lockup.

Original example:
PCIE1: connected as Root Complex
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
03:00.0 - 10b5:8112 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:00.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:01.0 - 10b5:8518 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
01:00.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b

Updated example:
PCIE1: connected as Root Complex
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
03:00.0 - 10b5:8112 - Bridge device
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
07:00.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:01.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

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pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW

This change does the following:
- Removes the printing of the PCI interrupt line value. This is
normally set to 0 by U-Boot on boo

pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW

This change does the following:
- Removes the printing of the PCI interrupt line value. This is
normally set to 0 by U-Boot on bootup and is rarely used during
everyday operation.

- Prints out the PCI function number of a device. Previously a device
with multiple functions would be printed identically 2 times, which is
generally confusing. For example, on an Intel 2 port gigabit Ethernet
card the following was displayed:
...
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
...

- Prints a text description of each device's PCI class instead of the
raw PCI class code. The textual description makes it much easier to
determine what devices are installed on a PCI bus.

- Changes the general formatting of the PCI device output.

Previous output:
PCIE1: connected as Root Complex
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d

Updated output:
PCIE1: connected as Root Complex
04:01.0 - 8086:1010 - Network controller
04:01.1 - 8086:1010 - Network controller
03:00.0 - 10b5:8112 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
08:00.0 - 1957:0040 - Processor
07:00.0 - 10b5:8518 - Bridge device
09:00.0 - 10b5:8112 - Bridge device
07:01.0 - 10b5:8518 - Bridge device
07:02.0 - 10b5:8518 - Bridge device
06:00.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
01:00.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d:00.0 - 1957:0040 - Processor
PCIE2: Bus 0c - 0d

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

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Merge branch 'master' of /home/wd/git/u-boot/master

Merge branch 'master' of git://git.denx.de/u-boot-marvell

Conflicts:
include/configs/km_arm.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-samsung

Merge branch 'master' of git://git.denx.de/u-boot-sparc

Merge branch 'master' of git://git.denx.de/u-boot-i2c

Merge branch 'for-wd-master' of git://git.denx.de/u-boot-pxa

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

pci: Add ability to re-enumerate PCI buses

Add a new 'pci enum' command which re-enumerates the PCI buses. This
command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful

pci: Add ability to re-enumerate PCI buses

Add a new 'pci enum' command which re-enumerates the PCI buses. This
command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful
in boards with FPGAs connected via PCI/PCIe, boards that support PCI
hot-plugging, or during PCI debug.

Also enable the 'pci enum' command for X-ES's Freescale-based boards.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>

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Merge remote branch 'origin/master' into next

Fix PCI_BASE_ADDRESS_5 handling in pci_hose_config_device()

Signed-off-by: FUJITA Kazutoshi <fujita@soum.co.jp>
Signed-off-by: <wd@denx.de>
Acked-by: Stefan Roese <sr@denx.de>

Merge branch 'evk1100-prep'

Merge branch 'mimc200'

Merge branch 'master' of git://git.denx.de/u-boot-video