| #
4a421a67 |
| 30-Nov-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-atmel
|
| #
1670c8c2 |
| 30-Nov-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
61bd2f75 |
| 04-Nov-2015 |
York Sun <yorksun@freescale.com> |
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disab
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
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| #
b939689c |
| 05-May-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
53626623 |
| 28-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga
|
| #
e536ab88 |
| 28-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
|
| #
cc555bd4 |
| 28-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
|
| #
86e6f7ea |
| 24-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fdt
|
| #
08442ec7 |
| 24-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
|
| #
3f6dcdb9 |
| 24-Apr-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
66869f95 |
| 19-Mar-2015 |
York Sun <yorksun@freescale.com> |
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
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| #
b79dadf8 |
| 10-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
README
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
57c6941b |
| 02-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-usb
|
| #
b9cb6482 |
| 02-Mar-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
fc834100 |
| 01-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
|
| #
00956eb5 |
| 01-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sh
|
| #
1606b34a |
| 25-Feb-2015 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
e32d59a2 |
| 06-Jan-2015 |
York Sun <yorksun@freescale.com> |
driver/ddr/fsl: Add sync of refresh
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Sign
driver/ddr/fsl: Add sync of refresh
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|
| #
03e664d8 |
| 06-Jan-2015 |
York Sun <yorksun@freescale.com> |
driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compat
driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
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|
| #
4b19b744 |
| 08-Oct-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-imx/master'
The single file conflict below is actually trivial.
Conflicts:
board/boundary/nitrogen6x/nitrogen6x.c
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| #
3cc83f9d |
| 07-Oct-2014 |
Minkyu Kang <mk7.kang@samsung.com> |
Merge branch 'uboot'
|
| #
1454ba8e |
| 07-Oct-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'
|
| #
be9f643a |
| 26-Sep-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'for-tom' of git://git.denx.de/u-boot-dm
|
| #
2c2277f1 |
| 26-Sep-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
|
| #
1d71efbb |
| 01-Aug-2014 |
York Sun <yorksun@freescale.com> |
driver/ddr: Restruct driver to allow standalone memory space
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either l
driver/ddr: Restruct driver to allow standalone memory space
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <yorksun@freescale.com>
show more ...
|