45e0908a | 07-Aug-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
fix hclk calculate error |
898309af | 17-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04 |
eff28274 | 16-Jul-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Revert "Revert "Merge branch 'feature/clk_dev' into aspeed-dev-v2019.04""
This reverts commit fd98b62831ed9249f1656f1760ddc354b2455eaa. |
fd98b628 | 16-Jul-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Revert "Merge branch 'feature/clk_dev' into aspeed-dev-v2019.04"
This reverts commit a1e27f4f7eed7f15b45d3cc85a58dc332937e46f, reversing changes made to 65287740cbb6a73fd83be1470f38cfc573741eeb. |
839df411 | 15-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] revise mac clock control |
fc9f12e6 | 15-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
fix clk and reset |
fd52be0b | 11-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] refactor the PLL configuration flow |
c7ebc30f | 11-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'feature/revise_dram' into aspeed-dev-v2019.04 |
10069884 | 09-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update sd clk cal |
5b5c3d44 | 09-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add comments |
d0bdd5f3 | 09-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
fix emmc clk |
6fa1ef3d | 08-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
add support 2 apb clk |
75ced45a | 05-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] use union to parse PLL divider setting |
577fcdae | 05-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] revise PLL paramter calculation.
the algorithm for calculating PLL parameters is not suitable for ast2600. Use pre-defined lookup table to ensure all candidates of the PLL parameters are gu
[update] revise PLL paramter calculation.
the algorithm for calculating PLL parameters is not suitable for ast2600. Use pre-defined lookup table to ensure all candidates of the PLL parameters are guaranteed by the IP provider.
show more ...
|
54f9cba1 | 04-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] correct MAC#3/#4 configuration |
b6a32f64 | 04-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'feature/ast2600_mac' into aspeed-dev-v2019.04 |
ed30249c | 04-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] revise MAC#1/#2 delay setting
now MAC#1 and MAC#2 can execute ping command successfully. |
c29e1cc8 | 03-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update |
4760b3f8 | 03-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add MAC default delay |
31a90994 | 03-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add default PLL lookup table |
894c19cf | 03-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] set MAC controller freq |
cc476ffc | 03-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add MAC clock setting |
bbbfb0c5 | 02-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update a/e/d/m/h pll |
369186fa | 13-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04 |
d35ac78c | 13-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update clk info for ast2500/ast2600 |