| #
b6832af8 |
| 30-Jan-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
|
| #
ac13eb5d |
| 17-Dec-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
board/T4240qds:Fix TLB and LAW size of NAND flash
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.
board/T4240qds:Fix TLB and LAW size of NAND flash
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.
So Update TLB and LAW size of NAND flash accordingly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|
| #
3e4d27b0 |
| 10-Nov-2012 |
Stefano Babic <sbabic@denx.de> |
Merge git://git.denx.de/u-boot
|
| #
a42c87f9 |
| 03-Nov-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-ti/master'
|
| #
f04821a8 |
| 27-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-imx/master'
|
| #
4c257613 |
| 26-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-atmel/master'
|
| #
c68436fa |
| 26-Oct-2012 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot-ti/master'
|
| #
71724830 |
| 22-Oct-2012 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fdt
|
| #
c7656bab |
| 22-Oct-2012 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
|
| #
ee52b188 |
| 11-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/t4qds: Add T4QDS board
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
S
powerpc/t4qds: Add T4QDS board
The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.
SERDES Connections
32 lanes grouped into four 8-lane banks
Two “front side” banks dedicated to Ethernet
Two “back side” banks dedicated to other protocols
DDR Controllers
Three independant 64-bit DDR3 controllers
Supports rates up to 2133 MHz data-rate
Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA
Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.
Detail information can be found in doc/README.t4qds
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
show more ...
|